View S1D15710_872053.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev.1.1c S1D15710 series technical manual
notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind aris ing out of any inaccuracies c ontained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyri ght infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. all other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ?seiko epson corporation 2005, all rights reserved.
technical manual S1D15710 series
notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind aristing out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export licence from teh ministry of international trade and industry or other approval from another government agency. all other product names mentioned herein are trademark and/or registered trademarks of their respective companies. ? seiko epson corporation 2004, all rights reserved.
configuration of product number devices s1 d 15710 d 00b0 00 packing specification specifications shape (d:chip, t:tcp, f:qfp) model number model name (d:lcd driver) product classification (s1:semiconductors)
S1D15710 series (rev. 1.1c) epson i contents 1. description .................................................................................................................. ................................. 1 2. features ..................................................................................................................... .................................... 1 3. block diagram ................................................................................................................ .............................. 2 4. pin layout ................................................................................................................... ................................... 3 5. pin description .............................................................................................................. .............................. 7 6. function description ......................................................................................................... ..................... 11 7. command description .......................................................................................................... ................... 29 8. command setting .............................................................................................................. ........................ 40 9. absolute maximum ratings ..................................................................................................... .............. 44 10. dc characteristics .......................................................................................................... ........................ 45 11. microprocessor (mpu) interface: reference .............................................................................. 57 12. connection between lcd drivers: reference ............................................................................. 58 13. lcd panel wiring: reference ................................................................................................. .............. 59 14. tcp pin layout .............................................................................................................. .............................. 60 15. tcp dimensions .............................................................................................................. ............................. 61 16. temperature sensor circuit .................................................................................................. ............. 62 17. notes ....................................................................................................................... ...................................... 65
S1D15710 series (rev. 1.1c) epson 1 1. description the S1D15710 series is a single-chip dot matrix liquid crystal display driver that can be connected directly to a microprocessor bus. eight-bit parallel or serial display data transmitted from the microprocessor is stored in the internal display data ram, and the chip generates liquid crystal drive signals, independently of the microprocessor. it has a on-chip 65 256-bit display data ram, and there is a one-to-one correspondence between the dot pixel on the liquid crystal panel pixels and internal ram bit. this feature ensures implementation of highly free display. the S1D15710 series incorporate 65 common output circuits and 224 segment output circuits. a single chip can drive a 65 224 dot display (capable of displaying 14 columns 4 rows with 16 16-dot kanji font). further, display capacity can be extended by designing two chips in a master/display configuration. since both the S1D15710 * 10 ** and S1D15710 * 11 ** have built-in analog temperature sensor circuits, systems can be build that can maintain appropriate liquid crystal contrast over a wide temperature range with microcomputer control without requiring such parts as thermostats. the S1D15710 series can read and write ram data with the minimum current consumption because it does not require any external operation clock. also it incorporates a lcd power supply featuring a very low current consumption, a lcd drive power voltage regulator resistor and a display clock cr oscillator circuit. this allows the display system of a high- performance for handy equipment to be realized at the minimum power consumption and minimum component configuration. 2. features direct display of ram data using the display data ram ram bit data ??.... goes on. ??.... goes off (at display normal rotation). ram capacity 65 256 = 16,640 bits liquid crystal drive circuit 65 circuits for the common output and 224 circuits for the segment output high-speed 8-bit mpu interface (both the 80 and 68 series mups can directly be connected.)/serial interface enabled abundant command functions display data read/write, display on/off, display normal rotation/reversal, page address set, display start line set, column address set, status read, power supply save display all lighting on/off, lcd bias set, read modify write, segment driver direction select, electronic control, v 5 voltage adjusting built-in resistance ratio set, static indicator, n line alternating current reversal drive, common output state selection, and built-in oscillator circuit on built-in static drive circuit for indicators (one set, blinking speed variable) built-in power supply circuit for low power supply liquid crystal drive booster circuit (boosting magnification - double, triple, quadruple, boosting reference power supply external input enabled) 3% high accuracy alternating current voltage adjusting circuit (temperature gradient: ?.05%/ c) built-in v 5 voltage adjusting resistor, built-in v 1 to v4 voltage generation split resistors, built-in electronic control function, and voltage follower built-in cr oscillator circuit (external clock input enabled) low power consumption built-in temperature sensor circuit (S1D15710d10b * and S1D15710d11b * ) power supplies logic power supply: v dd ?v ss = 1.8 to 5.5 v boosting reference power supply: v dd ?v ss = 1.8 to 6.0 v liquid crystal drive power supply: v 5 ?v dd = ?.5 to ?8.0 v wide operating temperature range ?0 to +85 c cmos process shipping form bare chip, tcp no light-resistant and radiation-resistant design are provided. series specification product name duty bias seg dr com dr v reg temperature shipping form gradient S1D15710d00b * 1/65 1/9, 1/7 224 65 C0.05%/ c bare chip S1D15710d10b * (*1) 1/65 1/9, 1/7 224 65 C0.05%/ c bare chip S1D15710d11b * (*2) 1/65 1/9, 1/7 224 65 C0.05%/ c bare chip S1D15710t00 ** 1/65 1/9, 1/7 224 65 C0.05%/ c tcp *1: the built-in power circuit has been upgraded so that liquid crystal displays having big load capacities can be driven. check the display and select if the display quality is inadequate even in high power mode of S1D15710d00b * . there are no methods for supplying liquid crystal drive power externally without using the built-in power circuit. in that case, select either the S1D15710d00b * or the S1D15710d11b * . *2: all specificationa are same as those of the S1D15710d00b * except for the temperature sensor circuit. 1. description
2 epson S1D15710 series (rev. 1.1c) 3. block diagram v ss v dd v 1 v 2 v 3 v 4 v 5 v out v ss2 v r v rs irs hpm cap1+ cap1 C cap2 C cap2+ cap3 C frs cls oscillator circuit display timing generator circuit line address i/o buffer fr cl sync dof m/s cs1 cs2 a0 rd (e) wr (r/w) p/s res d7 (si) d6 (scl) d5 d4 d3 d2 d1 d0 seg0 seg223 com0 com63 coms ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? coms com drivers seg drivers display data latch circuit display data ram 256 x 65 column address status command decoder interface bus holder shift register power supply circuit page address mpu 3. block diagram
S1D15710 series (rev. 1.1c) epson 3 item size unit xy chip size 16.65 2.90 mm chip thickness 0.625 mm bump pitch 69 (min.) m bump size pad no.1 to 117 85 85 m pad no.118 85 73 m pad no.119 to 151 85 47 m pad no.152 85 73 m pad no.153 73 85 m pad no.154 to 381 47 85 m pad no.382 73 85 m pad no.383 85 73 m pad no.384 to 416 85 47 m pad no.417 85 73 m bump height 17 (typ.) m 4. pin layout chip specification S1D15710 series (0, 0) y x 118 117 1 153 382 152 417 383 die no. d157ad 0b (as an example of S1D15710d00b * /d11b * ) 4. pin layout
4 epson S1D15710 series (rev. 1.1c) pad pin xy no. name 1 (nc) 7814 1293 2 sync 7677 3 frs 7541 4 test1 7404 5v dd 7268 6 test2 7131 7v ss 6995 8 test3 6855 9v dd 6718 10 test4 6582 11 v ss 6445 12 v ss 6309 13 v ss 6169 14 v dd 6033 15 v dd 5896 16 v dd 5760 17 v dd 5623 18 test5 5483 19 test5 5347 20 test6 5210 21 test6 5074 22 test7 4937 23 test7 4798 24 test8 4661 25 test8 4525 26 test9 4388 27 test9 4252 28 sync 4112 29 frs 3975 30 fr 3839 31 cl 3702 32 dof 3566 33 v ss 3429 34 cs1 3293 35 cs2 3156 36 v dd 3020 37 res 2883 38 a0 2747 39 v ss 2610 40 wr, r/w 2474 41 rd,e 2337 42 v dd 2201 43 d0 2064 44 d1 1928 45 d2 1791 46 d3 1655 47 d4 1518 48 d5 1382 49 d6 (scl) 1245 50 d7 (si) 1109 pad pin xy no. name 51 v dd 972 1293 52 v dd 838 53 v dd 704 54 v dd 571 55 v dd 437 56 v ss 303 57 v ss 169 58 v ss 35 59 v ss2 C 99 60 v ss2 C 233 61 v ss2 C 367 62 v ss2 C 501 63 v ss2 C 635 64 (nc) C 768 65 v out C 902 66 v out C 1036 67 cap3 CC 1170 68 cap3 CC 1304 69 (nc) C 1438 70 cap1+ C 1572 71 cap1+ C 1706 72 cap1 CC 1840 73 cap1 CC 1974 74 cap2 CC 2107 75 cap2 CC 2241 76 cap2+ C 2375 77 cap2+ C 2509 78 v ss C 2643 79 v ss C 2777 80 v rs C 2911 81 v rs C 3045 82 v dd C 3179 83 v dd C 3313 84 v 1 C 3446 85 v 1 C 3580 86 v 2 C 3714 87 v 2 C 3848 88 (nc) C 3982 89 v 3 C 4116 90 v 3 C 4250 91 v 4 C 4384 92 v 4 C 4518 93 v 5 C 4652 94 v 5 C 4785 95 (nc) C 4919 96 v r C 5053 97 v dd C 5187 98 test10 C 5321 99 v ss C 5455 100 test11 C 5589 pad pin xy no. name 101 v dd C 5723 1293 102 m/s C 5859 103 cls C 5996 104 v ss C 6132 105 c86 C 6269 106 p/s C 6405 107 v dd C 6542 108 hpm C 6678 109 v ss C 6815 110 irs C 6951 111 v dd C 7088 112 test12 C 7224 113 test13 C 7361 114 test14 C 7510 115 test15 C 7630 116 test16 C 7750 117 (nc) C 7869 118 (nc) C 8148 1295 119 com31 1209 120 com30 1137 121 com29 1064 122 com28 991 123 com27 919 124 com26 846 125 com25 773 126 com24 701 127 com23 628 128 com22 555 129 com21 483 130 com20 410 131 com19 337 132 com18 265 133 com17 192 134 com16 119 135 com15 47 136 com14 C 26 137 com13 C 99 138 com12 C 171 139 com11 C 244 140 com10 C 317 141 com9 C 389 142 com8 C 462 143 com7 C 535 144 com6 C 607 145 com5 C 680 146 com4 C 753 147 com3 C 825 148 com2 C 898 149 com1 C 971 150 com0 C 1043 pad central coordinates unit: m 4. pin layout
S1D15710 series (rev. 1.1c) epson 5 pad pin xy no. name 201 seg45 C 4579 C 1293 202 seg46 C 4510 203 seg47 C 4441 204 seg48 C 4372 205 seg49 C 4303 206 seg50 C 4234 207 seg51 C 4164 208 seg52 C 4095 209 seg53 C 4026 210 seg54 C 3957 211 seg55 C 3888 212 seg56 C 3819 213 seg57 C 3750 214 seg58 C 3681 215 seg59 C 3612 216 seg60 C 3543 217 seg61 C 3474 218 seg62 C 3405 219 seg63 C 3336 220 seg64 C 3267 221 seg65 C 3198 222 seg66 C 3129 223 seg67 C 3060 224 seg68 C 2991 225 seg69 C 2922 226 seg70 C 2853 227 seg71 C 2784 228 seg72 C 2715 229 seg73 C 2646 230 seg74 C 2577 231 seg75 C 2508 232 seg76 C 2439 233 seg77 C 2370 234 seg78 C 2301 235 seg79 C 2232 236 seg80 C 2163 237 seg81 C 2094 238 seg82 C 2025 239 seg83 C 1956 240 seg84 C 1886 241 seg85 C 1817 242 seg86 C 1748 243 seg87 C 1679 244 seg88 C 1610 245 seg89 C 1541 246 seg90 C 1472 247 seg91 C 1403 248 seg92 C 1334 249 seg93 C 1265 250 seg94 C 1196 pad pin xy no. name 251 seg95 C 1127 C 1293 252 seg96 C 1058 253 seg97 C 989 254 seg98 C 920 255 seg99 C 851 256 seg100 C 782 257 seg101 C 713 258 seg102 C 644 259 seg103 C 575 260 seg104 C 506 261 seg105 C 437 262 seg106 C 368 263 seg107 C 299 264 seg108 C 230 265 seg109 C 161 266 seg110 C 92 267 seg111 C 23 268 seg112 46 269 seg113 115 270 seg114 184 271 seg115 253 272 seg116 322 273 seg117 391 274 seg118 461 275 seg119 530 276 seg120 599 277 seg121 668 278 seg122 737 279 seg123 806 280 seg124 875 281 seg125 944 282 seg126 1013 283 seg127 1082 284 seg128 1151 285 seg129 1220 286 seg130 1289 287 seg131 1358 288 seg132 1427 289 seg133 1496 290 seg134 1565 291 seg135 1634 292 seg136 1703 293 seg137 1772 294 seg138 1841 295 seg139 1910 296 seg140 1979 297 seg141 2048 298 seg142 2117 299 seg143 2186 300 seg144 2255 pad pin xy no. name 151 coms C 8148 C 1116 152 (nc) C 1201 153 (nc) C 7906 C 1293 154 (nc) C 7823 155 (nc) C 7754 156 seg0 C 7685 157 seg1 C 7616 158 seg2 C 7547 159 seg3 C 7478 160 seg4 C 7409 161 seg5 C 7340 162 seg6 C 7271 163 seg7 C 7202 164 seg8 C 7133 165 seg9 C 7064 166 seg10 C 6995 167 seg11 C 6926 168 seg12 C 6857 169 seg13 C 6788 170 seg14 C 6719 171 seg15 C 6650 172 seg16 C 6581 173 seg17 C 6512 174 seg18 C 6442 175 seg19 C 6373 176 seg20 C 6304 177 seg21 C 6235 178 seg22 C 6166 179 seg23 C 6097 180 seg24 C 6028 181 seg25 C 5959 182 seg26 C 5890 183 seg27 C 5821 184 seg28 C 5752 185 seg29 C 5683 186 seg30 C 5614 187 seg31 C 5545 188 seg32 C 5476 189 seg33 C 5407 190 seg34 C 5338 191 seg35 C 5269 192 seg36 C 5200 193 seg37 C 5131 194 seg38 C 5062 195 seg39 C 4993 196 seg40 C 4924 197 seg41 C 4855 198 seg42 C 4786 199 seg43 C 4717 200 seg44 C 4648 unit: m 4. pin layout
6 epson S1D15710 series (rev. 1.1c) pad pin xy no. name 401 com49 8148 119 402 com50 192 403 com51 265 404 com52 337 405 com53 410 406 com54 483 407 com55 555 408 com56 628 409 com57 701 410 com58 773 411 com59 846 412 com60 919 413 com61 991 414 com62 1064 415 com63 1137 416 coms 1209 417 (nc) 1295 pad pin xy no. name 351 seg195 5776 C 1293 352 seg196 5845 353 seg197 5914 354 seg198 5983 355 seg199 6052 356 seg200 6121 357 seg201 6190 358 seg202 6259 359 seg203 6328 360 seg204 6397 361 seg205 6466 362 seg206 6535 363 seg207 6604 364 seg208 6673 365 seg209 6742 366 seg210 6811 367 seg211 6880 368 seg212 6949 369 seg213 7018 370 seg214 7087 371 seg215 7156 372 seg216 7225 373 seg217 7294 374 seg218 7364 375 seg219 7433 376 seg220 7502 377 seg221 7571 378 seg222 7640 379 seg223 7709 380 (nc) 7778 381 (nc) 7847 382 (nc) 7930 383 (nc) 8148 C 1201 384 com32 C 1116 385 com33 C 1043 386 com34 C 971 387 com35 C 898 388 com36 C 825 389 com37 C 753 390 com38 C 680 391 com39 C 607 392 com40 C 535 393 com41 C 462 394 com42 C 389 395 com43 C 317 396 com44 C 244 397 com45 C 171 398 com46 C 99 399 com47 C 26 400 com48 47 unit: m pad pin xy no. name 301 seg145 2324 C 1293 302 seg146 2393 303 seg147 2462 304 seg148 2531 305 seg149 2600 306 seg150 2669 307 seg151 2739 308 seg152 2808 309 seg153 2877 310 seg154 2946 311 seg155 3015 312 seg156 3084 313 seg157 3153 314 seg158 3222 315 seg159 3291 316 seg160 3360 317 seg161 3429 318 seg162 3498 319 seg163 3567 320 seg164 3636 321 seg165 3705 322 seg166 3774 323 seg167 3843 324 seg168 3912 325 seg169 3981 326 seg170 4050 327 seg171 4119 328 seg172 4188 329 seg173 4257 330 seg174 4326 331 seg175 4395 332 seg176 4464 333 seg177 4533 334 seg178 4602 335 seg179 4671 336 seg180 4740 337 seg181 4809 338 seg182 4878 339 seg183 4947 340 seg184 5017 341 seg185 5086 342 seg186 5155 343 seg187 5224 344 seg188 5293 345 seg189 5362 346 seg190 5431 347 seg191 5500 348 seg192 5569 349 seg193 5638 350 seg194 5707 4. pin layout
S1D15710 series (rev. 1.1c) epson 7 5. pin description power supply pin lcd power supply circuit pin pin name i/o description number of pins cap1+ o boosting capacitor positive side connecting pin. connects 2 a capacitor between the pin and cap1 C pin. cap1 C o boosting capacitor negative side connecting pin. connects 2 a capacitor between the pin and cap1+ pin. cap2+ o boosting capacitor positive side connecting pin. connects 2 a capacitor between the pin and cap2 C pin. cap2 C o boosting capacitor negative side connecting pin. connects 2 a capacitor between the pin and cap2+ pin. cap3 C o boosting capacitor negative side connecting pin. connects 2 a capacitor between the pin and cap1+ pin. v out i/o boosting output pin. connects a capacitor between the pin and v ss2 .2 v r i voltage adjusting pin. applies voltage between v dd and v 5 using 1 a split resistor. valid only when the v 5 voltage adjusting built-in resistor is not used (irs=low) do not use vr when the v 5 voltage adjusting built-in resistor is used (irs=high) v 1 1/9 ? v 5 1/7 ? v 5 v 2 2/9 ? v 5 2/7 ? v 5 v 3 7/9 ? v 5 5/7 ? v 5 v 4 8/9 ? v 5 6/7 ? v 5 pin name i/o description number of pins v dd power commonly used with the mpu power supply pin v cc .12 supply v ss power 0 v pin connected to the system ground (gnd) 9 supply v ss2 power boosting circuit reference power supply for liquid crystal drive 5 supply v rs power external input pin for liquid crystal power supply voltage supply adjusting circuit 2 they are set to open v 1 , v 2 power multi-level power supply for liquid crystal drive. the voltage 10 v 3 , v 4 supply specified according to liquid crystal cells is impedance-converted v 5 by a split resistor or operation amplifier (op amp) and applied. the potential needs to be specified based on v dd to establish the relationship of dimensions shown below: v dd (=v 0 ) v 1 v 2 v 3 v 4 v 5 master operation when the power supply is on, the following voltages are applied to v 1 ~ v 4 from the built-in power supply circuit. the selection of the voltages is determined using the lcd bias set command. 5. pin description
8 epson S1D15710 series (rev. 1.1c) system bus connecting pins pin name i/o description number of pins d7 to d0 i/o an 8-bit bidirectional data bus is used to connect an 8-bit or 16-bit 8 (si) standard mpu data bus. (scl) when the serial interface is selected (p/s=low), d7: serial data entry pin (si) d6: serial clock input pin (scl) in this case, d0 to d5 are set to high impedance. when chip select is in the non-active state, d0 to d7 are set to high impedance. a0 i normally the lowest order bit of the mpu address bus is connected 1 to discriminate data / commands. a0=high: indicates that d0 to d7 are display data. a0=low: indicates that d0 to d7 are control data. res i initialized by setting res to low. 1 reset operation is performed at the res signal level. cs1 i chip select signal. when cs1=low and cs2=high, this signal 2 cs2 becomes active and the input/output of data/commands is enabled. rd i ? when the 80 series mpu is connected, active low is set. 1 (e) pin that connects the rd signal of the 80 series mpu. when this signal is low, the S1D15710 series data bus is set in the output state . ? when the 68 series mpu is connected, active high is set. 68 series mpu enable clock input pin wr i ? when the 80 series mpu is connected, active low is set. 1 (r/w) pin that connects the wr signal of the 80 series mpu. the data bus signal is latched on the leading edge of the wr signal. ? when the 68 series mpu is connected, read/write control signal input pin r/w=high: read operation r/w=low: write operation frs o output pin for static drive 1 used together with the sync pin c86 i mpu interface switching pin 1 c86=high: 68 series mpu interface c86=low: 80 series mpu interface p/s i switching pin for parallel data entry/serial data entry 1 p/s=high: parallel data entry p/s=low: serial data entry according to the p/s state, the following table is given. when p/s=low, d0 to d5 are set to high impedance. d0 to d5 can be high, low, or open . rd(e) and wr (r/w) are fixed to high or low. for the serial data entry, ram display data cannot be read. p/s data/ data read/write serial clock command high a0 d0 to d7 rd, wr low a0 si (d7) write-only scl (d6) 5. pin description
S1D15710 series (rev. 1.1c) epson 9 pin name i/o description number of pins cls i pin that selects the validity/invalidity of the built-in oscillator circuit 1 for display clocks. cls=high: built-in oscillator circuit valid cls=low: built-in oscillator circuit invalid (external input) when cls=low, display clocks are input from the cl pin. when the S1D15710 series is used for the master/slave configuration, each of the cls pins is set to the same level together. m/s i pin that selects the master/slave operation for the S1D15710 series. 1 the liquid crystal display system is synchronized by outputting the timing signal required for the liquid crystal display for the master operation and inputting the timing signal required for the liquid crystal display for the slave operation. m/s=high: master operation m/s=low: slave operation according to the m/s and cls states, the following table is given. cl i/o display clock i/o pin 1 according to the m/s and cls states, the following table is given. when the S1D15710 series is used for the master/slave configuration, each cl pin is connected. fr i/o liquid crystal alternating current signal i/o pin 1 m/s=high: output m/s=low: input when the S1D15710 series is used for the master/slave configuration, each fr pin is connected. sync i/o liquid crystal synchronizing current signal i/o pin 2 m/s=high: output m/s=low: input when the S1D15710 series is used for the master/slave configuration, each sync pin is connected. dof i/o liquid crystal display blanking control pin 1 m/s=high: output m/s=low: input when the S1D15710 series is used for the master/slave configuration, each dof pin is connected. irs i v 5 voltage adjusting resistor selection pin 1 irs=high: built-in resistor used irs=low: built-in resistor not used. the v 5 voltage is adjusted by the v r pin and stand-alone split resistor. valid only at master operation. the pin is fixed to high or low at slave operation. hpm i power supply control pin of the power supply circuit for liquid 1 crystal drive hpm=high: normal mode hpm=low: high power supply mode valid only at master operation. the pin is fixed to high or low at slave operation. m/s cls cl high high output low input low high input low input display clock master slave built-in oscillator circuit used high high external input low low m/s cls oscillator power supply cl fr sync frs dof circuit circuit high high valid valid output output output output output low invalid valid input output output output output low high invalid invalid input input input output input low invalid invalid input input input output input 5. pin description
10 epson S1D15710 series (rev. 1.1c) liquid crystal drive pin pin name i/o description number of pins seg0 o output pins for the lcd segment drive. contents of the display 224 to ram and fr signal are combined to select a desired level among seg223 v dd , v 2 , v 3 and v 5 . com0 output pins for the lcd common drive. scan data and fr signal 64 to are combined to select a desired level among v dd , v 1 , v 4 and v 5 . com63 coms o indicator dedicated com output pin 2 set to open when not used when coms is used for the master/slave configuration, the same signal is output to both the master and slave. output voltage ram data fr display display reversal normal operation high high v dd v 2 high low v 5 v 3 low high v 2 v dd low low v 3 v 5 power save v dd scanning data fr output voltage high high v 5 high low v dd low high v 1 low low v 4 power save v dd test pin pin name i/o description number of pins test1 to 4 i/o fix the pin to high. 4 to use a built-in temperature sensor circuit in the S1D15710 * 00 ** / S1D15710 * 11 ** , see 16, temperature sensor circuit. test10 i fix it to high for the S1D15710 * 00 ** /S1D15710 * 11 ** ; fix it to 1 low for S1D15710 * 10 ** . test11to13 i/o ic chip test pin. fix the pin to high. 3 test5 to 9, i/o ic chip test pin. take into consideration so that the capacity of 13 14 to 16 lines cannot be exhausted by setting the pin to open. 5. pin description
S1D15710 series (rev. 1.1c) epson 11 6. function description mpu interface selection of interface type the S1D15710 series transfers data through 8-bit bidirectional data buses (d7 to d0) or serial data input (si). by setting the polarity of the p/s pin to either high or low, the 8-bit parallel data entry or serial data entry can be selected as listed in table 1. table 1 p/s cs1 cs2 a0 rd wr c86 d7 d6 d5 to d0 high: parallel data entry cs1 cs2 a0 rd wr c86 d7 d6 d5 to d0 low: serial data entry cs1 cs2 a0 si scl (hz) fix ?to high or low . hz indicates the high impedance state. parallel interface when the parallel interface is selected (p/s=high), the s1d15705 series can directly be connected to the mpu bus of either the 80 or 68 series mpu by setting the c86 pin to high or low as listed in table 2. table 2 c86 cs1 cs2 a0 rd wr d7 to d0 high: 68 series mpu bus cs1 cs2 a0 e r/w d7 to d0 low: 80 series mpu bus cs1 cs2 a0 rd wr d7 to d0 in addition, the data bus signal can be identified according to the combinations of the a0, rd (e), wr (r/w) signals as listed in table 3. table 3 common 68 series 80 series a0 r/w rd wr function 1 1 0 1 display data read 1 0 1 0 display data write 0 1 0 1 status read 0 0 1 0 control data write (command) 6. function description
12 epson S1D15710 series (rev. 1.1c) chip select the S1D15710 series has two chip select pins cs1 and cs2 and enables the mpu interface or serial interface only when cs1=low and cs2=high. when chip select is in the non-active state, d0 to d7 are in the high impedance state and the a0, rd, and wr inputs become invalid. when the serial interface is selected, the shift register and counter are reset. display data ram and internal register access since the S1D15710 series access viewed from the mup side satisfies the cycle time and does not require the wait time, high-speed data transfer is enabled. the S1D15710 series performs a kind of inter-lsi pipeline processing through the bus holder attached to the internal data bus when it performs the data transfer with the mpu. for example, when data is written on the display data ram, the data is first held in the bus holder and written serial interface when the serial interface is selected (p/s=low), the serial data entry (si) and serial clock input(scl) can be accepted with the chip in the non-active state (cs1=low or cs2=high. the serial interface consists of an 8-bit shift register and a 3-bit counter. serial data is fetched from the serial data entry pin in the order of d7, d6, ...., and d0 on the leading edge of the serial clock and converted into 8-bit parallel data on the leading edge of the 8th serial clock, then processed. whether to identify that the serial data entry is display data or command is judged by the a0 input, and a0=high indicates display data and a0=low indicates the command. after the chip is set to the non-active state, the a0 input is read and identified at the timing on the 8 n-th leading edge of the serial clock. figure 1 shows the signal chart of the serial interface. on the display data ram up to the next data write cycle. further, when the mpu reads the contents of display data ram, the read data at the first data read cycle (dummy) is held in the bus holder and read on the system bus from the bus holder up to the next data read cycle. the read sequence of the display data ram is restricted. when the address is set, note that the specified address data is not output to the subsequent read instruction and output at the second data read. therefore single dummy read is required after the address set and write cycle. figure 2 shows this relationship. busy flag when the busy flag is ?? it indicates that the S1D15710 series is performing an internal operation, and only the status read instruction can be accepted. the busy flag is output to the d7 pin using the status read command. if the cycle time ( t cyc ) is ensured, the mpu throughput can be improved greatly since this flag needs not be checked before each command. figure 1 when the chip is in the non-active state, both the shift register and counter are reset to the initial state. cannot be read for the serial interface. for the scl signal, pay careful attention to the terminating reflection of lines and external noise. the operation confirmation using actual equipment is recommended. cs1 cs2 si scl a0 d7 1234567891011121314 d6 d5 d4 d3 d2 d7 d6 d5 d4 d3 d2 d1 d0 6. function description
S1D15710 series (rev. 1.1c) epson 13 ?write n n n+1 n+2 n+3 n+1 n+2 n+3 wr mpu internal timing data latch bus holder write signal ?read n n n n+1 n+2 increment n+1 preset n n n n+1 n+2 data read #n+1 data read #n dummy read address set #n wr rd data address preset read signal column address bus holder mpu internal timing figure 2 6. function description
14 epson S1D15710 series (rev. 1.1c) display data ram display data ram this display data ram stores display dot data and consists of 65 (8 pages one 8 bit + 1) 256 bits. desired bits can be accessed by specifying page and column addresses. since the mpu display data d7 to d0 correspond to the common direction of the liquid crystal display, the restrictions at display data transfer is reduced and the display configuration with the high degree of freedom can easily be obtained when the S1D15710 series is used for the multiple chip configuration. besides, the read/write operation to the display data ram is performed through the i/o buffer from the mpu side independently of the liquid crystal drive signal read. therefore even when the display data ram is asynchronously accessed during liquid crystal display, the access will not have any adverse effect on the display such as flickering. page address circuit as shown in figure 4, the page address of the display data ram is specified using the page address set command. to access the data using a new page, the page address is respecified. the page address 8 (d3,d2,d1,d0=1,0,0,0) is an indicator dedicated ram area and only the display data d0 is valid. column address circuit as shown in figure 4, the display data ram column address is specified by the column address set command. the specified column address is incremented by +1 at every input of display data read/write command. this allows the mpu to access the display data continuously. incrementation of the column address is stopped by ffh. when display data is accessed continuously, the column address continues to specify the ffh after access of the ffh. it should be noted that the column address ffh display data is accessed repeatedly. the column address and page address are independent of each other. therefore, when shifting from the column of page 0 to the column of page 1, for example, it is necessary to specify each of the page address and column address again. furthermore, as shown in table 4, the ad command (segment driver direction select command) can used to reverse the correspondence between the display data ram column address and segment output. this allows constraints on ic layout to be minimized at the time of lcd module assembling. table 4 line address circuit when displaying contents of the display data ram, the line address circuit is used for specifying the corresponding addresses. see figure 4. using the display start line address set command, the top line is normally selected (when the common output state is normal, com0 is output. and, when reversed outputs com63). for the display area of 65 lines is secured starting from the specified display start line address in the address incrementing direction. dynamically changing the line address using the display start line address set command enables screen scrolling and page change. figure 3 d0 d1 d2 d3 d4 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 display data ram com0 com1 com2 com3 com4 liquid crystal display seg output seg0 seg223 adc 0 0 (h) column address df (h) (d0) 1 ff (h) column address 20 (h) 6. function description
S1D15710 series (rev. 1.1c) epson 15 figure 4 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 coms 0 0 0 0 page 0 0 0 0 1 page 1 0 0 1 0 page 2 0 0 1 1 page 3 0 1 0 0 page 4 0 1 0 1 page 5 0 1 1 0 page 6 0 1 1 1 page 7 1000 page 8 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 ff fe fd fc fb fa f9 f8 00 01 02 03 04 05 06 07 seg218 seg217 seg218 seg219 seg220 seg221 seg222 seg223 27 26 25 24 23 22 21 20 d8 d9 da db dc dd de df lcd out adc column address 1 d0 0 d0 64 lines page address d3 d2 d1 d0 data line address com output common output state: normal rotation when setting the display start line to one channel start the 65th line is accessed independently of the display start line address. 6. function description
16 epson S1D15710 series (rev. 1.1c) display data latch circuit the display data latch circuit is a latch that temporarily stores the display data output from the display data ram to the liquid crystal drive circuit. since the display normal rotation/reversal, display on/off, and display all lighting on/off commands control the data in this latch, the data within the display data ram is not changed. oscillator circuit this oscillator circuit is a cr type oscillator and generates display clocks. the oscillator circuit is valid only when m/s=high and cls=high and starts oscillation after the built-in oscillator circuit on command is entered. when cls=low, the oscillation is stopped and the display clocks are entered from the cl pin. display timing generator circuit this display timing generator circuit generates timing signals from the display clocks to the line address circuit and the display latch circuit. it latches the display data to the display data latch circuit and outputs it to the segment drive output pin by synchronizing to the display clocks. the read operation of display data to the liquid crystal drive circuit is completely independent of the access to the display data ram from the mpu. therefore even when the display data ram is asynchronously accessed during liquid crystal display, the access will not have any adverse effect on the display such as flickering. the circuit also generates the internal common timing, liquid crystal alternating current signal (fr), and synchronous signal (sync) from the display clocks. as shown in figure 5, the fr normally generates the drive waveforms in the 2-frame alternating current drive system to the liquid crystal drive circuit. it can generate n-line reversal alternating current drive waveforms by setting data (n-1) to the n-line reversal drive register. if a display quality problem such as crosstalk occurs, it can be improved by using the n-line reversal alternating current drive waveforms. determine the number of lines (n) to which alternating current is applied by actually displaying the liquid crystal. snyc is a signal that synchronizes the line counter and common timing generator circuit to the sync signal output side ic. therefore the sync signal becomes a waveform at a duty ratio of 50% that synchronizes to the frame synchronization. when the S1D15710 series is used for the multiple chip configuration, the slave side needs to supply the display timing signals (fr, sync, cl, and dof) from the master side. table 5 shows the state of fr, sync, cl, or dof. 2-frame alternating current drive waveforms figure 5 64 cl fr sync com0 v dd v dd v dd v 1 v 1 v 4 v 5 v 4 v 2 v 3 v 5 v 5 com1 ram data segn 65 1 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6 table 5 operation mode fr sync cl dof master built-in oscillator circuit valid (cls=high) output output output output (m/s=high) built-in oscillator circuit invalid (cls=low) output output input output slave built-in oscillator circuit valid (cls=high) input input input input (m/s=low) built-in oscillator circuit invalid (cls=low) input input input input 6. function description
S1D15710 series (rev. 1.1c) epson 17 common output state selection circuit the S1D15710 series can set the scanning direction of the com output using the common output state selection command (see figure 6). therefore the ic assignment restrictions at lcd module assembly are reduced. table 6 figure 6 n-line reversal alternating current drive waveforms (example of n=5: when the line reversal register is set to 4) 64 cl fr sync com0 v dd v dd v dd v 1 v 1 v 4 v 5 v 4 v 2 v 3 v 5 v 5 com1 ram data segn 65 1 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6 liquid crystal drive circuit this liquid crystal drive circuit is 289 sets of mutiplexers that generate quadruple levels for liquid crystal drive. it outputs the liquid crystal drive voltage that corresponds to the combinations of the display data, com scanning signal, and fr signal. figure 6 shows examples of the seg and com output waveforms. state com scanning direction normal rotation com 0 com 63 reversal com 63 com 0 6. function description
18 epson S1D15710 series (rev. 1.1c) figure 7 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 fr com0 com1 com2 seg0 seg1 seg2 com0 C seg0 com0 C seg1 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 5 v 4 v 3 C v 3 C v 4 C v 5 v 2 v 1 v dd C v 1 C v 2 v 5 v 4 v 3 C v 3 C v 4 C v 5 v 2 v 1 v dd C v 1 C v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v ss 6. function description
S1D15710 series (rev. 1.1c) epson 19 table 7 description of controlling bits using the power control set command item state ? ? d2 boosting circuit control bit on off d1 voltage adjusting circuit (v adjusting circuit) control bit on off d0 voltage follower circuit (v/f circuit) control bit on off table 8 reference combinations status of use d2 d1 d0 boosting v adjusting v/f external boosting circuit circuit circuit voltage input system pin 1 built-in power 1 1 1 o o o v ss2 used supply used 2 v adjusting circuit 0 1 1 x o o v out , v ss2 open and v/f circuit only 3 v/f circuit only 0 0 1 x x o v 5 , v ss2 open 4 external power 0 0 0 x x x v 1 to v 5 open supply only the boosting system pin indicates the cap1+, cap1? cap2+, cap2? or cap3?pin. although the combinations other than those listed in the above table are also possible, they cannot be recommended because they are not actual use methods. power supply circuit this power supply circuit is a low power supply consumption one that generates the voltage required for the liquid crystal drive and consists of a boosting circuit, voltage adjusting circuit, and voltage follower circuit. it is valid only at master operation. the power supply circuit on/off controls the boosting circuit, voltage adjusting circuit, and voltage follower circuit using the power supply control set command, respectively. therefore, it can also use the partial functions of the external power supply and built-in power supply together. table 7 lists the functions that control 3-bit data using the power control set command and table 8 lists the reference combinations. boosting circuit the boosting circuit incorporated in the S1D15710 series enables the quadruple boosting, triple boosting, and double boosting of the v dd ?v ss2 potential. for the quadruple boosting, the v dd ? v ss2 potential is quadruple-boosted to the negative side and output to the v out pin by connecting the capacitor c1 between cap1+ ? and cap1? between cap2+ ? and cap2? between cap1+ ? and cap3? and between v ss2 ? and v out . for the triple boosting, the v dd ? v ss2 potential is triple-boosted to the negative side and output to the v out pin by connecting the capacitor c1 between cap1+ ? and cap1? between cap2+ ? and cap2? and between v ss2 ? and v out and strapping both cap3?and v out pins. for the double boosting, the v dd ? v ss2 potential is doubly boosted to the negative side and output to the v out pin by connecting the capacitor c1 between cap1+ ? and cap1? and between v ss2 ? , setting cap2+ to open, and v out and strapping cap2? cap3? and v out pins. figure 8 shows the relationships of boosting potential. 6. function description
20 epson S1D15710 series (rev. 1.1c) voltage adjusting circuit the boosting voltage generated in v out outputs the liquid crystal drive voltage v 5 through the voltage adjusting circuit. since the S1D15710 series incorporates a high-accuracy constant power supply, 64-step electronic control function, and v 5 voltage adjusting resistor, a high- accuracy voltage adjusting circuit can eliminate and save parts. (a) when using the v 5 voltage adjusting built-in resistor the liquid crystal power supply voltage v 5 can be controlled only using the command without an external resistor and the light and shade of liquid crystal display be adjusted by using the v 5 voltage adjusting built-in resistor and the electronic control function. the v 5 voltage can be obtained according to expression a-1 within the range of |v 5 |<|v out |. (expression a-1) v rb ra v rb ra v vv ev reg ev reg 5 1 11 162 1 162 =+ ? ? ? ? ? =+ ? ? ? ? ? ? ? ? ? ? =? () ? [] figure 8 set the v ss2 ?voltage range so that the voltage of the v out pin cannot exceed the absolute maximum ratings. v ss2 v out cap3 C cap1+ cap1 C cap2 C cap2+ c1 c1 c1 c1 + + + S1D15710 S1D15710 quadruple boosting circuit v ss2 v out cap3 C cap1+ cap1 C cap2 C cap2+ c1 c1 c1 + + + triple boosting circuit v ss2 v out cap3 C cap1+ cap1 C cap2 C cap2+ open c1 c1 + + double boosting circuit S1D15710 v dd = 0v v ss2 = C 3v v out = 4 x v ss2 = C 12v quadruple boosting p otential relationshi p v dd = 0v v ss2 = C 3v v out = 3 x v ss2 = C 9v triple boosting p otential relationshi p v dd = 0v v ss2 = C 5v v out = 2 x v ss2 = C 10v double boosting p otential relationshi p 6. function description
S1D15710 series (rev. 1.1c) epson 21 v reg is a constant voltage source within an ic, and the value at ta=25 c is constant as listed in table 9. table 9 device temperature unit v reg unit gradient internal C 0.05 [%/ c] C 2.1 [v] power supply indicates an electronic control command value. setting data in a 6-bit electronic control register enters one state among 64 states. table 10 lists the values of based on the setup of the electronic control register. table 10 d5 d4 d3 d2 d1 d0 000000 63 000001 62 000010 61 111101 2 111110 1 111111 0 rb/ra indicates the v 5 voltage adjusting built-in resistance ratio and can be adjusted into eight steps using the v 5 voltage adjusting built-in resistance ratio set command. the reference values of the (1+rb/ra) ratio are obtained as listed in table 11 by setting 3-bit data in the v 5 voltage adjusting built-in resistance ratio register. table 11 (reference values) for the internal resistance ratio, a manufacturing dispersion of up to 7% should be taken into account. when not within the tolerance, adjust the v 5 voltage by externally mounting ra and rb. figure 10 show the v 5 voltage reference values per temperature gradient device based on the values of the v 5 voltage adjusting built-in resistance ratio register and electronic control register at ta=25 c. figure 9 v ev (constant voltage source + electronic control) built-in ra + C built-in rb v dd v 5 register device per temperature gradient [unit: %/ c] d2 d1 d0 ?.05 000 4.5 001 5.0 010 5.5 011 6.0 100 6.5 101 7.0 110 7.6 111 8.1 6. function description
22 epson S1D15710 series (rev. 1.1c) figure 10 S1D15710 ***** temperature gradient = C 0.05%/ c v 5 voltage based on the values of v 5 voltage adjusting built-in resistance ratio register and electronic control register C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 0 v 5 [v] 00h 18h 30h 3fh electric volume resister 111 S1D15710 ***** 000 001 010 011 100 101 110 v 5 voltage adjusting built-in resistance ratio registers (d2, d1, and d0) from figure 8 and expression a-1. table 12 register description d5 d4 d3 d2 d1 d0 v 5 voltage adjusting CCC 010 electronic control 1 0 0 1 0 1 in this case, table 13 lists the v 5 voltage variable range and pitch width using the electronic control function. table 13 v 5 min. typ. max. unit variable range C 11.6 to C 9.3 to C 7.1 [v] pitch width 67 [mv] 6. function description
S1D15710 series (rev. 1.1c) epson 23 set the value of the electronic control register as the intermediate value (d5, d4, d3, d2, d1, d0) = (1,0,0,0,0,0). from the foregoing we can establish the expression: from expression b-1, it follows that (expression b-2) also, suppose the current applied to ra?and rb?is 5 a. (expression b-2) it follows that therefore from expressions b-2 and b-3, we have in this case, table 14 lists the v 5 voltage variable range and pitch width using the electronic control function. = = 31 21 vv reg ? v rb ra v v rb ra reg 5 11 162 91 1 31 162 21 =+ ? ? ? ? ?? ? ? ? ? ? ?=+ ? ? ? ? ?? ? ? ? ? ?? () ' ' ' ' . ra rb m ''. += 18 ? rb ra ra k rb k ' ' . ' ' = =? =? 43 340 1460 v ev (constant voltage source + electronic control) v r stand-alone ra' + C stand-alone rb v dd v 5 figure 11 (b) when using the external resistor (not using the v 5 voltage adjusting built-in resistor) 1 the liquid crystal power supply voltage v 5 can also be set by adding the resistors (ra and rb ) between v dd and v r and between v r and v 5 without the v 5 voltage adjusting built-in resistor (irs pin=low). also in this case, the liquid crystal power supply voltage v 5 can be controlled using the command and the light and shade of liquid crystal display can be adjusted by using the electronic control function. the v 5 voltage can be obtained from expression b- 1 by setting the external resistors ra and rb within the range of |v 5 | < |v out |. (expression b-1) v rb ra v rb ra v vv ev reg ev reg 5 1 11 162 1 162 =+ ? ? ? ? ? =+ ? ? ? ? ? ? ? ? ? ? =? () ? [] ' ' ' ' table 14 v 5 min. typ. max. unit variable range C 11.1 to C 9.0 to C 6.8 [v] pitch width 67 [mv] (c) when using the external resistor (not using the v 5 voltage adjusting built-in resistor) 2 in the use of the above-mentioned external resistor, the liquid crystal power supply voltage v 5 can also be set by adding the resistors to finely adjust ra and rb . also in this case, the liquid crystal power supply voltage v 5 can be controlled using the command and the light and shade of liquid crystal display can be adjusted by using the electronic control function. the v 5 voltage can be obtained from the following expression c-1 by setting the external resistors r 1 , r 2 (variable resistors), and r 3 within the range of |v 5 | < |v out | and finely adjusting r 2 ( ? r 2 ). (expression c-1) v rr r rr v rr r rr v vv ev reg ev reg 5 32 2 12 32 2 12 1 11 162 1 162 =+ +? +? ? ? ? ? ? ? ? =+ +?? +? ? ? ? ? ? ? ? ? ? ? ? ? =? () ? [] ? 6. function description
24 epson S1D15710 series (rev. 1.1c) set the value of the electronic control register as the intermediate value (d5, d4, d3, d2, d1, d0) = (1,0,0,0,0,0). from the foregoing we can establish the expression: = =? 31 21 vv reg . when ? r 2 =0 ? , to obtain v 5 = 9 v from expression c- 1, it follows that ?=+ + ? ? ? ? ? ? ?? ? ? ? ? ?? () 11 1 1 31 162 21 32 1 v rr r . (expression c-2) when ? r 2 =r 2 , to obtain v 5 = 7v, it follows that ?=+ + ? ? ? ? ? ? ?? ? ? ? ? ?? () 71 1 31 162 21 3 12 v r rr . (expression c-3) also, suppose the current applied between v dd and v 5 is 5 a. rr r m 123 18 ++= ? . (expression c-4) it follows that therefore from expressions c-2, c-3, and c-4, we have rk rk rk 1 2 3 162 278 1363 =? =? =? at this time, the v 5 voltage variable range and notch width based on electronic volume function are given in the following table when v 5 = 9 v by r 2 is assumed: figure 12 v ev (constant voltage source + electronic control) stand-alone r1 ? r 2 v r stand-alone r3 + C v dd v 5 rb' ra' stand-alone r2 stand-alone r2 table 15 v 5 min. typ. max. unit variable range C 11.1 to C 9.0 to C 6.8 [v] pitch width 67 [mv] when using the v 5 voltage adjusting built-in resistor or electronic control function, the state where at least the v 5 voltage adjusting circuit and voltage follower circuit are operated together needs to be set using the power control set command. also when the boosting circuit is off, the voltage needs to be applied from v out . the v r pin is valid only when the v 5 voltage adjusting built-in resistor (irs pin=low). set the v r pin to open when using the v 5 voltage adjusting built-in resistor (irs pin=high). since the v r pin has high input impedance, noise must be taken into consideration such as for short and shielded lines. liquid crystal voltage generator circuit the v 5 voltage is resistor-split within an ic and generates the v 1 , v 2 , v 3 , and v 4 potentials required for the liquid crystal drive. further, the v 1 , v 2 , v 3 , and v 4 potentials are impedance- converted by the voltage follower and supplied to the liquid crystal drive circuit. using the bias set command allows you to select a desired bias ratio from 1/9 or 1/7. high power mode the power supply circuit incorporated in the S1D15710 series has the ultra-low power consumption (normal mode: hpm=high). therefore the display quality 6. function description
S1D15710 series (rev. 1.1c) epson 25 may be deteriorated in large load liquid crystal or panels. in this case, the display quality can be improved by setting hpm pin=low (high power mode). whether to use the power supply circuit in this mode should need the display confirmation by actual equipment. also, if improvement is insufficient even for the high power mode setting, use either the S1D15710d10b * or supply liquid crystal drive power externally. in either case, be sure to check the display thoroughly. command sequence when the built-in power supply is turned off to turn off the built-in power supply, set it in the power save state and then turn off the power supply according to the command sequence shown in figure 13 (procedure). figure 13 procedure step1 step2 description (command, state) power save turning off the built -in power supply command address d7 1 d6 0 d5 1 d4 0 power save command (both stand-by and slee p can be useal ) d3 1 d2 0 d1 0 d0 0 1 v dd v dd v dd v ss c 1 v ss2 cap3 C cap1+ cap1 C cap2+ cap2 C v out v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s c 1 c 1 c 2 c 2 c 2 c 2 c 2 S1D15710 v dd v ss c 1 v ss2 cap3 C cap1+ cap1 C cap2+ cap2 C v out v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s c 1 c 1 c 1 c 1 r 3 r 2 r 1 c 2 c 2 c 2 c 2 c 2 S1D15710 (1) when using the v 5 voltage adjusting built-in resistor (example of v ss2 =v ss , quadruple boosting) 1 all the built-in power supply used (2) when not using the v 5 voltage adjusting built-in resistor (example of v ss2 =v ss , quadruple boosting) 6. function description
26 epson S1D15710 series (rev. 1.1c) figure 14 (1) when using the v 5 voltage adjusting built-in resistor (2) when not using the v 5 voltage adjusting built-in resistor 2 only the voltage adjusting circuit and v/f circuit used v dd v dd v ss v ss2 cap3 C cap1+ cap1 C cap2+ cap2 C v out v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s r 3 r 2 r 1 c 2 c 2 c 2 c 2 c 2 S1D15710 external power supply v dd v dd v ss external power supply v ss2 cap3 C cap1+ cap1 C cap2+ cap2 C v out v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s c 2 c 2 c 2 c 2 c 2 S1D15710 4 only the external power supply used depending on all external power supplies 3 only the v/f circuit used v dd v dd v ss external power supply v ss2 cap3 C cap1+ cap1 C cap2+ cap2 C v out v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s c 2 c 2 c 2 c 2 c 2 S1D15710 v dd v dd external power supply v ss v ss2 cap3 C cap1+ cap1 C cap2+ cap2 C v out v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s s1d157510 item setting value unit c 1 1.0 to 4.7 f c 2 0.01 to 1.0 f common reference setting example at v 5 = 8 to 12 v variable 6. function description
S1D15710 series (rev. 1.1c) epson 27 *1 since the v r terminal input impedance is high, use short leads and shielded lines. when the v r terminal is not used, means should be taken to prevent capacitance of the line or others from being applied. *2 c 1 and c 2 are determined according to the size of the lcd panel. set a value so that the liquid crystal drive voltage can be stable. [setting example] turn on the v 5 adjusting circuit and the v/f circuit and apply external voltage. display lcd heavy load patterns like lateral stripes and determine c 2 so that the liquid crystal drive voltages (v 1 to v 5 ) can be stable. then turn on all built-in power supplies and determine c 1 . *3 capacity is connected in order to stabilize voltage between v dd and v ss power supplies. *4 when the built-in v/f circuit is used to drive an lcd panel with heavy alternating or direct current load, we recommend that external resistance be connected in order to stabilize v/f outputs, or electric potentials, v 1 , v 2 , v 3 and v 4 . adjust resistance value r 4 to the optimal level by checking driving waveform displayed on the lcd. reference setting: r 4 = 0.1 to 1.0 [m ? ] figure 15 v dd v dd v 1 v 2 v 3 v 4 v 5 r 4 r 4 r 4 r 4 c 2 c 2 S1D15710 series c 2 c 2 c 2 *5 precautions when installing the cog when installing the cog, it is necessary to duly consider the fact that there exists a resistance of the ito wiring occurring between the driver chip and the externally connected parts (such as capacitors and resistors). by the influence of this resistance, non-conformity may occur with the indications on the liquid crystal display. therefore, when installing the cog design the module paying sufficient considerations to the following three points. 1. suppress the resistance occurring between the driver chip pin to the externally connected parts as much as possible. 2. suppress the resistance connecting to the power supply pin of the driver chip. 3. make various cog module samples with different ito sheet resistance to select the module with the sheet resistance with sufficient operation margin. also, as for this driver ic, pay sufficient attention to the following points when connecting to external parts for the characteristics of the circuit. 1. connection to the boosting capacitors the boosting capacitors (the capacitors connecting to respective cap pins and capacitor being inserted between v out and v ss2 ) of this ic are being switched over by use of the transistor with very low on-resistance of about 10 ? . however, when installing the cog, the resistance of ito wiring is being inserted in series with the switching transistor, thus dominating the boosting ability. consequently, the boosting ability will be hindered as a result and pay sufficient attention to the wiring to respective boosting capacitors. 2. connection of the smoothing capacitors for the liquid crystal drive the smoothing capacitors for the liquid crystal driving potentials (v 1 . v 2 , v 3 and v 4 ) are indispensable for liquid crystal drives not only for the purpose of mere stabilization of the voltage levels. if the ito wiring resistance which occurs pursuant to installation of the cog is supplemented to these smoothing capacitors, the liquid crystal driving potentials become unstable to cause non- conformity with the indications of the liquid crystal display. therefore, when using the cog module, we definitely recommend to connect reinforcing resistors externally. reference value of the resistance is 100k ? to 1m ? . meanwhile, because of the existence of these reinforcing resistors, current consumption will increase. 6. function description
28 epson S1D15710 series (rev. 1.1c) 20. test mode reset on the other hand, when using the reset command, only the items 11 to 20 of the above-mentioned initial setting are executed. when the power is turned on, the initialization using the res pin is required. after the initialization using the res pin, each input pin needs to be controlled normally. besides, when the mpu control signal has high impedance, overcurrent may be applied to an ic. after turning on the power, take action so that the input pin cannot have high impedance. the S1D15710 series discharge electric charges of v 5 and v out at res pin is set to the low level. if external power supplies for driving lcd are used, do not input external power while the res pin is set to the low level to prevent short-circuiting between the external power supplies and v dd . reference circuit examples reset circuit when the res input is set to the low level, this lsi enters each of the initial setting states 1. display off 2. display normal rotation 3. adc select: normal rotation (adc command d0=0) 4. power control register: (d2,d1,d0)=(0,0,0) 5. register data clear within serial interface 6. lcd power supply bias ratio: 1/9 bias 7. n-line alternating current reversal drive reset 8. power saving clear 9. display all lighting off: (display all lighting on/off command d0=low) 10. built-in oscillator circuit stopped 11. static indicator off static indicator register: (d1,d2)=(0,0) 12. read modify write off 13. display start line set to the first line 14. column address set to address 0 15. page address set to page 0 16. common output state normal rotation 17. v 5 voltage adjusting built-in resistance ratio register: (d2,d1,d0)=(0,0,0) 18. electronic control register set mode reset electronic control register* (d5, d4, d3, d2, d1, d0) = (1,0,0,0,0,0) 19. n-line alternating current reversal register: (d3, d2, d1, d0) = (0, 0, 0, 0) exemplary connection diagram 1. exemplary connection diagram 2. indicated below is an exemplary connection diagram of external resistors. please make sufficient evaluation work for the display statuses with any connection tests. v dd v dd v 1 v 2 v 3 v 4 v 5 r 4 r 4 r 4 r 4 c 2 c 2 S1D15710 series c 2 c 2 c 2 v dd v dd v 1 v 2 v 3 v 4 v 5 r 4 r 4 c 2 c 2 S1D15710 series c 2 c 2 c 2 6. function description
S1D15710 series (rev. 1.1c) epson 29 7. command description the S1D15710 series identifies data bus signals according to the combinations of a0, rd(e), and wr(r/w). since the interpretation and execution of commands are performed only by the internal timing independently of external clocks, the S1D15710 performs high-speed processing that does not require busy check normally. the 80 series mpu interface starts commands by inputting low pulses to the rd pin at read and to the wr pin at write operation. the 68 series mpu interface enters the read state when high is input to the r/w pin. it enters the write state when low is input to the same pin. it starts commands by inputting high pulses to the e pin (for the timing, see the timing characteristics of chapter 10). therefore the 68 series mpu interface differs from the 80 series mpu interface in that rd(e) is set to 1 (h) at status read and display data read in the command description and command table. the command description is given below by taking the 80 series mpu interface as an example. when selecting the serial interface, enter sequential data from d 7 . command description (1) display on/off this command specifies display on/off. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 setting 01010101111 display on 0 display off for display off, the segment and common drivers output the v dd level. (2) display start line set this command specifies the display start line address of the display data ram shown in figure 4. the display area is displayed for 65 lines from the specified line address to the line address increment direction. when this command is used to dynamically change the line address, the vertical smooth scroll and page change are enabled. for details, see the line address circuit of function description . er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 line address 01001000000 0 000001 1 000010 2 111110 62 111111 63 7. command description
30 epson S1D15710 series (rev. 1.1c) (3) page address set this command specifies the page address that corresponds to the low address when accessing the display data ram shown in figure 4 from the mpu side. the display data ram can access desired bits when the page address and column address are specified. even when the page address is changed, the display state will not be changed. for details, see the page address circuit of function description . er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 page address 01010110000 0 0001 1 0010 2 0111 7 1000 8 (4) column address set this command specifies the column address of the display data ram shown in figure 4. the column address is split into two sections (higher 4-bits and lower 4-bits) when it is set (set continuously in principle). each time the display data ram is accessed, the column address automatically increments (+), making it possible for the mpu to continuously read and write the display data. the column address increment is stopped at ffh, and the ffh is specified continuously. this must be noted when you want to access continuously. in this case, the page address is not changed continuously. for details, see column address circuit in function description. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 high-order bit 0100001a7a6a5a4 low-order bit 0 a3a2a1a0 a7 a6 a5 a4 a3 a2 a1 a0 column address 00000000 0 00000001 1 00000010 2 11111110 254 11111111 255 (5) status read er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 busy adc on/off reset 0000 7. command description
S1D15710 series (rev. 1.1c) epson 31 busy when busy=1, indicates an internal operation being done or reset. the command cannot be accepted until busy=0 is reached. however, if the cycle time is satisfied, the command needs not be checked. adc indicates the correspondence relationship between the column address and segment driver. 0: reversal (column address 199 C n ? seg n) 1: normal rotation (column address n ? seg n) (reverses the polarity of adc command.) on/off on/off: specifies display on/off 0: display on 1: display off (reverses the polarity of display on/off command.) reset indicates the res signal or that initial setting is being done using the reset command. 0: operating state 1: resetting (6) display data write this command writes 8-bit data to the specified address of the display data ram. since the column address is automatically incremented by 1 after the data is written, the mpu can successively write the display data. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 write data (7) display data read this command reads the 8-bit data in the specified address of the display data ram. since the column address is automatically incremented by 1 after the data is written, the mpu can successively read the data consisting of multiple words. besides, immediately after the column address is set, dummy read is required one time. for details, see the description of the display data ram and internal register access of function description . when using the serial interface, the display cannot be read. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 read data (8) adc select (segment driver direction select) this command can reverse the correspondence relationship between the column address of the display ram data shown in figure 4 and the segment driver output. therefore the order of the segment driver output pin can be reversed using the command. after the display data is written and read, the column address is incremented by 1 according to the column address of figure 4. for details, see the column address circuit of function description . er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 setting 01010100000 cl ockwise (normal rotation) 1 counterclockwise (reversal) 7. command description
32 epson S1D15710 series (rev. 1.1c) (9) display normal rotation/reversal this command can reversal display lighting and non-lighting without overwriting the contents of display data ram. in this case, the contents of display data ram are held. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 setting 01010100110 lcd on potential (normal rotation) ram data high 1 lcd on potential (reversal) ram data low (10) display all lighting on/off this command can forcedly make all display set in the lighting state irrespective of the contents of display data ram. in this case, the contents of display data ram are held. this command has priority over the display normal rotation/reversal command. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 setting 01010100100 normal display state 1 display all lighting (11) lcd bias set this command selects the bias ratio of the voltage required for liquid crystal drive. the command is valid when the v/ f circuit of the power supply circuit is operated. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 selected state 01010100010 1/9 bias 1 1/7 bias (12) read modify write this command is used together with the end command. once this command is entered, the column address can be incremented by 1 only using the display data write command instead of being changed using the display read command. this state is held until the end command is entered. when the end command is entered, the column address returns to the address when the read modify write command is entered. this function can reduce the load of the mpu when repeatedly changing data for a specific display area such as a blinking cursor. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100000 * the commands other than display data read/write can be used even in read modify write mode. however, the column address set command cannot be used. 7. command description
S1D15710 series (rev. 1.1c) epson 33 sequence for cursor display figure 16 page address set column address set dummy read data read data write data processing end yes no is the change terminated? read modify write (13) end this command resets the read modify write mode and returns the column address to the mode initial address. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011101110 figure 17 n n+m ? ? ? n+3 n+2 n+1 n column address read modify write mode set end return (14) reset this command initializes display start line, column address, page address, common output state, v 5 voltage adjusting built-in resistance ratio, electronic control, and static indicator and resets the read modify write mode and test mode. this will not have any effect on the display data ram. for details, see the reset of function description . reset operation is performed after the reset command is entered. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100010 the initialization when the power is applied is performed using the reset signal to the res pin. the reset command cannot be substituted for the signal. 7. command description
34 epson S1D15710 series (rev. 1.1c) (15) common output state selection this command can select the scanning direction of the com output pin. for details, see the common output state selection circuit of function description . er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 selected state 01011000* * * normal rotation com0 com63 1 reversal com63 com0 *: invalid bit (16) power control set this command sets the function of the power supply circuit. for details, see the power supply circuit of function description . er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 selected state 010001010 boosting circuit: off 1 boosting circuit: on 0 v adjusting circuit: off 1 v adjusting circuit: on 0 v/f circuit: off 1 v/f circuit: on (v/f circuit: voltage follower circuit, v adjusting circuit: voltage adjusting circuit) (17) v 5 voltage adjusting built-in resistance ratio set this command sets the v 5 voltage adjusting built-in resistance ratio. for details, see the power supply circuit of function description . er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 rb to ra ratio 01000100000 small 001 010 110 1 1 1 large (18) electronic control (2-byte command) this command controls the liquid crystal drive voltage v 5 output from the voltage adjusting circuit of the built-in liquid crystal power supply and can adjust the light and shade of liquid crystal display. since this command is a 2-byte command that is used together with the electronic control mode set command and electronic control register set command, always use both the commands consecutively. electronic control mode set entering this command validates the electronic control register set command. once the electronic control mode is set, the commands other than the electronic control register set command cannot be used. this state is reset after data is set in the register using the electronic control register set command. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01010000001 7. command description
S1D15710 series (rev. 1.1c) epson 35 electronic control register set this command is used to set 6-bit data in the electronic volume register to allow the liquid crystal drive voltage v 5 to enter one-state voltage value among 64-state voltage values. after this command is entered and the electronic control register is set, the electronic control mode is reset. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 | v 5 | 010* *000000 small 010* *000001 010* *000010 010* *111110 0 1 0 * * 1 1 1 1 1 1 large *: invalid bit when not using the electronic control function, set (1,0,0,0,0,0). sequence of the electronic control register set figure 18 (19) static indicator (2-byte command) this command controls the indicator display of the static drive system. the static indicator display is controlled only using this command, and this command is independent of other display control commands. the static indicator is used to connect the sync pin to one of its liquid crystal drive electrodes and the frs pin to the other. for the electrodes used for the static indicator, the pattern separated from the electrodes for dynamic drive are recommended. when this pattern is too adjacent, the deterioration of liquid crystal and electrodes may be caused. since the static indicator on command is a 2-byte command that is used together with the static indicator register set command, always use both the commands consecutively. (the static indicator off command is a 1-byte command.) static indicator on/off entering the static indicator on command validates the static indicator register set command. once the static indicator on command is entered, the commands other than the static indicator register set command cannot be used. this state is reset after the data is set in the register using the static indicator register set command. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 static indicator 01010101100 off 1on electronic control mode set electronic control register set electronic control mode reset yes no is the change terminated? 7. command description
36 epson S1D15710 series (rev. 1.1c) static indicator register set this command sets data in the 2-bit static indicator register and sets the blinking state of the static indicator. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 indicator display state 010******00 off 0 1 on (blinks at an interval of approximately 0.5 second.) 1 0 on (blinks at an interval of approximately one second.) 1 1 on (goes on at all times.) *: invalid bit sequence of static indicator register set figure 19 static indicator on static indicator register set yes no is the change terminated? (static indicator mode reset) (20) power save this command makes the static indicator enter the power save state and can greatly reduce the power consumption. the power save state consists of the sleep state and stand-by state. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 power save state 01010101000 stand-by state 1 sleep state the operating state before the display data and power save activation is held in the sleep and stand-by states, and the display data ram can also be accessed from the mpu. sleep state this command stops all the operations of lcd display systems, and can reduce the power consumption approximate to the static current when they are not accessed from the mpu. the internal state in the sleep state is as follows: (1) the oscillator circuit and the lcd power supply circuit are stopped. (2) all liquid crystal drive circuit is stopped and the segment and common drivers output the v dd level. 7. command description
S1D15710 series (rev. 1.1c) epson 37 stand-by state this command stops the operation of the duty lcd display system and operates only the static drive system for indicators. consequently the minimum current consumption required for the static drive is obtained. the internal state in the stand-by state is as follows: (1) the lcd power supply circuit is stopped. the oscillator circuit is operated. (2) the duty drive system liquid crystal drive circuit is stopped and the segment and common drivers output the v dd level. the static drive system is operated. * when using external power supplies, it is recommended that the function of the external power supply circuit should be stopped at power save activation. for example, when providing each level of the liquid crystal drive voltage using a stand-alone split resistor circuit, it is recommended that the circuit which cuts off the current applied to the split resistor circuit should be added at power save activation. the S1D15710 series has the liquid crystal display blanking control pin dof and is set to low at power save activation. the function of the external power supply circuit can be stopped using the dof output. (21) power save reset this command resets the power save state and returns the state before power save activation. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100001 (22) n-line reversal drive register set this command sets the number of reversal lines of the liquid crystal drive in the register. 2 to 16 lines can be set. for details, see the display timing generator circuit of function description . er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 line of reversal lines 01000110000 0001 2 0010 3 1110 15 1111 16 (23) n-line reversal drive reset this command resets the n-line reversal alternating current drive and returns to the normal 2-frame reversal alternating current drive system. the value of the n-line reversal alternating current drive register is not changed. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100100 (24) built-in oscillator circuit on this command starts the operation of the built-in cr oscillator circuit. this command is valid only for the master operation (m/s=high) and built-in oscillator circuit valid (cls=high). er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01010101011 7. command description
38 epson S1D15710 series (rev. 1.1c) (25) nop non-operation er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100011 (26) test ic chip test command. do not use this command. if the test command is used incorrectly, it can be reset by setting the res input to low or by using the reset command or nop. er/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101111 **** *: invalid bit (note) although the S1D15710 series holds the command operating state, it may change the internal state if excessive foreign noise is entered. such action that suppresses the generation of noise and prevents the effect of noise needs to be taken on installation and systems. besides, to prevent sudden noise, it is recommended that the operating state should periodically be refreshed. 7. command description
S1D15710 series (rev. 1.1c) epson 39 table 16 S1D15710 series commands command code command a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function (1) display on/off 0 1 0 1 0101110 lcd display on/off 1 0: off, 1: on (2) display start line set 0 1 0 0 1 display start address sets the display start line address of the display ram. (3) page address set 0 1 0 1 0 1 1 page sets the page address of address the display ram. (4) column address set 0 1 0 0 0 0 1 high order sets the high-order four bits of high-order bit column the column address of the display address ram. column address set 0 1 0 0 0 0 0 low order sets the low-order four bits of low-order bit column the column address of the display address ram. (5) status read 0 0 1 status 0 0 0 0 reads the status information. (6) display data read 1 1 0 write data writes data on the display ram. (7) display data write 1 0 1 read data reads data from the display ram. (8) adc select 0 1 0 1 0100000 supports the seg output of 1 the display ram address. 0: normal rotation, 1: reversal (9)display normal 0 1 0 10100110 lcd display normal rotation/ rotation/reversal 1 reversal 0: normal rotation, 1: reversal (10) display all lighting 0 1 0 1 0100100 display all lighting on/off 1 0: normal display, 1: all on (11) lcd bias set 0 1 0 1 0100010 sets the lcd drive voltage bias ratio. 1 0: 1/9, 1: 1/7 (12) read modify write 0 1 0 1 1100000 incr ements the column address. at write operation: by 1, at read: 0 (13) end 0 1 0 1 1101110 resets read modify write. (14) reset 0 1 0 1 1100010 internal resetting (15) common output state 0 1 0 1 1000* * * selects the scanning direction of selection the com output. 1 0: normal rotation, 1: reversal (16) power control set 0 1 0 0 0101 o perating selects the state of the built-in state power supply (17) v 5 voltage adjusting internal 0 1 0 0 0100 resistance selects the state of the built-in resistance ratio set ratio setting resistance ratio (rb/ra). (18) electronic control 0 1 0 1 0000001 mode set electronic control 0 1 0 * * electronic sets the v 5 output voltage register set control value in the electronic register. (19) static indicator on/off 0 1 0 1 0101100 0: off, 1: on 1 static indicator 0 1 0 * * * * * * state sets the blinking state. register set (20) power save 0 1 0 1 0101000 m oves to the power save state. 1 0: stand-by, 1: sleep (21) power save reset 0 1 0 1 1100001 resets power save. (22) n-line reversal drive 0 1 0 0 0 1 1 number of sets the number of line register set reversal line reversal drive lines. (23) n-line reversal drive reset 0 1 0 1 1100100 resets the line reversal drive. (24) built-in oscillator 0 1 0 1 0101011 s tarts the operation of the built-in circuit on cr oscillator circuit. (25) nop 0 1 0 1 1100011 non-operation command (26) test 0 1 0 1 1 1 1 ****do not use the ic chip test command. *: invalid bit 7. command description
40 epson S1D15710 series (rev. 1.1c) 8. command setting instruction setup: reference (1) initial setting notes: reference items *1: if external power supplies for driving lcd are used, do not supply voltage on v out or v 5 pin during the period when res = low. instead, input voltage after releasing the reset state. 6. function description reset circuit *2: the contents of ddram are not defined even in the initial setting state after resetting. 6. function description section reset circuit *3: 7. command description item (24) built-in oscillator circuit on *4: 7. command description item (11) lcd bias set *5: 7. command description item (8) adc select *6: 7. command description item (15) common output state selection *7: 6. function description section display timing generator circuit , 7. command description item (22) n-line reversal register set *8: 6. function description section power supply circuit and 7. command description item (17) v 5 voltage adjusting built-in resistance ratio set *9: 6. function description section power supply circuit and 7. command description item (18) electronic control *10: 6. function description section power supply circuit and 7. command description item (16) power control set turn on the v dd - v ss power supply in the res pin=low *1 power supply regulated initial setting state (default) *2 end of initial setting function setting by command input (set by user) (11) lcd bias set *4 (8) adc select *5 (15) common output state selection *6 (22) n-line reversal register set *7 (when the n-line alternating current reversal drive is used) function setting by command input (set by user) (17) v 5 voltage adjusting built-in resistance ratio set *8 (18) electronic control *9 function setting by command input (set by user) (24) built-in oscillator circuit on *3 (the built-in cr oscillator circuit is used) function setting by command input (set by user) (16) power control set *10 reset the reset state (res pin=high) 8. command setting
S1D15710 series (rev. 1.1c) epson 41 (2) data display notes: reference items *11: 7. command description item (2) display start line set *12: 7. command description item (3) page address set *13: 7. command description item (4) column address set *14: the contents of ddram is not defined after completing initial setting. enter data in each ddram to be used for display. 7. command description item (6) display data write *15: avoid activating the display function with entering space characters as the data if possible. 7. command description item (1) display on/off (3) refresh *16 notes: reference items *16: it is recommended that the operating modes and display contents be refreshed periodically to prevent the effect of unexpected noise. end of data display end of initial setting function setting by command input (set by user) (2) display start line set *11 (3) page address set *12 (4) column address set *13 function setting by command input (set by user) (1) display on/off *15 function setting by command input (set by user) (6) display data write *14 a desired mode set all commands again. write in the display data ram again. 8. command setting
42 epson S1D15710 series (rev. 1.1c) (4) power *17 notes: reference items *17: this ic is a v dd v ss power system circuit controlling the lcd driving circuit for the v dd v 5 power system. shutting of power with voltage remaining in the v dd v 5 power system may cause uncontrolling voltage to be output from the seg and com pins. follow the power off sequence. *18: 7. command description item (20) power saving *19: when external power supplies for driving lcd are used, turn all external power supplies off before entering reset state. 6. function description item reset circuit *20: the threshold voltage of the lcd panel is about 1 [v]. when the internal power supply circuit is used, discharge time t h from the start of resetting to the voltage between v dd and v 5 being reduced to 1 volt depends on capacitor c2 to be connected between v 1 v 5 and v dd . figure 5 shows the reference values. any desired state function setting by command input (set by user) (20) power save *18 set the time interval after the point when reset state has attained and the point when v dd C v ss power is shut off ( t l ) so that electric potentials, v1 through v 5 , attain values lower than the threshold voltage displayed on the lcd panel. *20 reset state (res pin=low) *19 v dd C v ss power off 100 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1 v 5 voltage discharge time [ms] capacity c2 [ f] figure 20 set up t l so that the relationship, t l > t h , is maintained. a state of t l < t h may cause faulty display. 8. command setting
S1D15710 series (rev. 1.1c) epson 43 v dd v dd v 1 v 2 v 3 v 4 v 5 res seg com power off power saving 1.8 [v] as power (v dd C v ss ) is shut off, it becomes impossible to fix output. at or under vth on lcd. use 1.0 [v] as a reference. t l t h figure 21 v dd v dd v 1 v 2 v 3 v 4 v 5 res seg com power off t l t h 1.8 [v] as power (v dd C v ss ) is shut off, it becomes unable to fix output. at or under vth on lcd. use 1.0 [v] as a reference. take action so that the relationship, t l > t h , is maintained by measures such as making the trailing characteristic longer. if command control is disabled when power is off, take action so that the relationship, t l > t h , is maintained by measures such as making the trailing characteristic of power (v dd v ss ) longer. figure 22 8. command setting
44 epson S1D15710 series (rev. 1.1c) 9. absolute maximum ratings table 17 v ss =0 v unless specified otherwise item symbol specification value unit power supply voltage v dd C 0.3 to +7.0 v power supply voltage (2) C 7.0 to +0.3 (based on v dd ) at triple boosting v ss2 C 6.0 to +0.3 at quadruple boosting C 4.5 to +0.3 power supply voltage (3) (based on v dd )v 5 , v out C 22.0 to +0.3 power supply voltage (4) (based on v dd )v 1 , v 2 , v 3 , v 4 v 5 to +0.3 input voltage v in C 0.3 to v dd +0.3 output voltage v o C 0.3 to v dd +0.3 operating temperature t opr C 40 to +85 c storage temperature tcp t str C 55 to +100 bare chip C 55 to +125 figure 23 (notes) 1. the values of the v ss2 , v 1 to v 5 , and v out voltages are based on v dd =0 v. 2. the v 1 , v 2 , v 3 , and v 4 voltages must always satisfy the condition of v dd v 1 v 2 v 3 v 4 v 5 . 3. insure that voltage levels v ss2 and v out are always such that the relationship of v dd v ss v ss2 v out is maintained. 4. when lsi is used exceeding the absolute maximum ratings, the lsi may be damaged permanently. besides, it is desirable that the lsi should be used in the electrical characteristics condition for normal operation. if this condition is exceeded, the lsi may malfunction and have an adverse effect on the reliability of the lsi. v dd v dd v ss2 , v 1 ~ v 4 v 5 , v out v cc gnd v ss S1D15710 side system (mpu) side 9. absolute maximum ratings
S1D15710 series (rev. 1.1c) epson 45 10. dc characteristics table 18 v ss =0 v, v dd =3.0 v 10%, and ta= 40 to +85 c specification value applicable item symbol condition min. typ. max. unit pin operating r ecommended v dd 2.7 3.3 v v dd *1 voltage operation (1) operable v dd 1.8 5.5 v dd *1 operating r ecommended v ss2 (based on v dd ) C 3.3 C 2.7 v ss2 voltage operation (2) operable v ss2 (based on v dd ) C 6.0 C 1.8 v ss2 operating operable v 5 (based on v dd ) C 18.0 C 4.5 v 5 *2 voltage operable v 1 , v 2 (based on v dd )0.4 v 5 v dd v 1 , v 2 (3) operable v 3 , v 4 (based on v dd )v 5 0.6 v 5 v 3 , v 4 high level input voltage v ihc 0.8 v dd v dd *3 low level input voltage v ilc v ss 0.2 v dd *3 high level output voltage v ohc i oh = C 0.5ma 0.8 v dd v dd *4 low level output voltage v olc i ol =0.5ma v ss 0.2 v dd *4 input leak current i li v in =v dd or v ss C 1.0 1.0 a*5 output leak current i lo C 3.0 3.0 *6 liquid crystal driver r on ta=25 cv 5 = C 14.0v 2.0 3.5 k ? segn on resistance (based on v dd )v 5 = C 8.0v 3.2 5.4 comn *7 static current consumption i ssq 0.01 5 av ss , v ss2 output leak current i 5q v 5 = C 18.0v (based on v dd ) 0.01 15 v 5 input pin capacity c in ta=25 c, f=1mhz 5.0 8.0 pf oscillating built-in f osc ta=25 c 182226khz*8 frequency oscillation external input f cl 4.5 5.5 6.5 cl *8 table 19 specification value applicable item symbol condition min. typ. max. unit pin input voltage v ss2 at triple boosting C 6.0 C 1.8 v v ss2 (based on v dd ) v ss2 at quadruple boosting C 5.0 C 1.8 v ss2 (based on v dd ) boosting output voltage v out (based on v dd ) C 20.0 v out voltage adjusting circuit v out (based on v dd ) C 20.0 C 6.0 v out operating voltage v/f circuit operating v 5 (based on v dd ) C 18.0 C 4.5 v 5 *9 voltage reference voltage v reg0 ta=25 c, C 0.05%/ c C 2.04 C 2.10 C 2.16 *10 [*: see page 49.] built-in power supply circuit 10. dc characteristics
46 epson S1D15710 series (rev. 1.1c) dynamic current consumption value (1) during display operation and built-in power supply off current values dissipated by the whole ic when the external power supply is used table 20 display all white ta=25 c specification value item symbol condition min. typ. max. unit remarks S1D15710d00b * i dd v dd =5.0v, v 5 C v dd = C 11.0v 25 42 a *11 /d11b * (1) v dd =3.0v, v 5 C v dd = C 11.0v 25 42 dynamic current consumption value (2) during display operation and built-in power supply on current values dissipated by the whole ic containing the built-in power supply circuit table 22 display all white ta=25 c specification value item symbol condition min. typ. max. unit remarks S1D15710 i dd v dd =5.0v, triple boosting normal mode 92 154 a *12 d00b * /d11b * (2) v 5 C v dd = C 11.0v high power mode 242 405 v dd =3.0v, quadruple boosting normal mode 129 216 v 5 C v dd = C 11.0v high power mode 310 518 S1D15710d10b * v dd =5.0v, triple boosting normal mode 135 225 v 5 C v dd = C 11.0v high power mode 288 480 v dd =3.0v, quadruple boosting normal mode 176 294 v 5 C v dd = C 11.0v high power mode 363 605 table 21 display checker pattern ta=25 c specification value item symbol condition min. typ. max. unit remarks S1D15710d00b * i dd v dd =5.0v, v 5 C v dd = C 11.0v 38 64 a *11 /d11b * (1) v dd =3.0v, v 5 C v dd = C 11.0v 38 64 table 23 display checker pattern ta=25 c specification value item symbol condition min. typ. max. unit remarks S1D15710 i dd v dd =5.0v, triple boosting normal mode 132 221 a *12 d00b * /d11b * (2) v 5 C v dd = C 11.0v high power mode 280 468 v dd =3.0v, quadruple boosting normal mode 167 279 v 5 C v dd = C 11.0v high power mode 350 585 S1D15710d10b * v dd =5.0v, triple boosting normal mode 178 297 v 5 C v dd = C 11.0v high power mode 330 550 v dd =3.0v, quadruple boosting normal mode 220 367 v 5 C v dd = C 11.0v high power mode 406 677 current consumption at power save v ss =0 v and v dd =3.0 v 10% table 24 ta=25 c specification value item symbol condition min. typ. max. unit remarks sleep state i dds1 0.01 5 a stand-by state i dds2 48 [*: see page 49.] 10. dc characteristics
S1D15710 series (rev. 1.1c) epson 47 [reference data 1] dynamic current consumption (1) external power supply used and lcd being displayed [reference data 2] dynamic current consumption (2) built-in power supply used and lcd being displayed condition: built-in power supply off external power supply used v 5 v dd = 11.0 v display pattern: all white/ checker ta = 25 c remarks: *11 condition: built-in power supply on quadruple boosting v 5 v dd = 11.0 v normal mode display pattern: all white/ checker ta = 25 c remarks: *12 [*: see page 49.] v dd [v] i dd (1) (i ss + i 5 ) [ a] checker all white 50 40 30 20 10 0 02468 v dd [v] i dd (2) [ a] S1D15710d00b * /d11b * display checker S1D15710d00b * /d11b * display all white 250 200 150 100 50 0 02468 S1D15710d10b * display checker S1D15710d10b * display all white figure 24 figure 25 10. dc characteristics
48 epson S1D15710 series (rev. 1.1c) figure 27 [reference data 3] dynamic current consumption (3) during access indicates the current consumption when the checker pattern is always written at f cyc . only i dd (1) when not accessed condition: built-in power supply off and external power supply used v dd v ss = 3.0 v, v 5 v dd = 11.0 v ta = 25 c v ss and v 5 system operating voltage ranges remarks: *2 [*: see page 49.] [reference data 4] f cyc [mhz] i dd (3) [ma] 10 1 0.1 0.01 0.001 0.01 0.1 1 10 v dd [v] v 5 - v dd [v] C 20 C 15 C 10 C 5 0 02468 1.8 3.6 5.5 C 7.2 C 18 C 4.5 S1D15710 series operation area figure 26 10. dc characteristics
S1D15710 series (rev. 1.1c) epson 49 table 25 item f cl f fr when built-in oscillator f osc f osc circuit used 4 4*65 when built-in oscillator external input (f cl )f cl circuit not used 65 (f fr indicates the alternating current cycle of the liquid crystal and does not indicate that of the fr signal.) [reference items marked by *] *1 the wide operating voltage range is not warranted. however, when there is a sudden voltage change during mpu access, it cannot be warranted. *2 for the v dd and v 5 operating voltage ranges, see figure 27. these ranges are applied when using the external power supply. *3 a0, d0 to d5, d6 (scl), d7 (si), rd (e), wr (r/w), cs1, cs2, cls, cl, fr, m/s, c86, p/s, dof, res, irs and hpm pins *4 d0 to d7, fr, frs, dof and cl pins *5 a0, rd (e), wr (r/w), cs1, cs2, cls, m/s, c86, p/s, res, irs and hpm pins *6 applied when d0 to d5, d6 (scl), d7 (si), cl, fr, and dof pins are in the high impedance state *7 resistance value when the 0.1 v voltage is applied between the output pin segn or comn and power supply pins (v 1 , v 2 , v 3 , and v 4 ). specified within the range of operating voltage (3) r on = 0.1 v/ ? i ( ? i indicates the current applied when 0.1 v is applied between the power on.) *8 for the relationship between the oscillating frequency and frame frequency. the specification value of the external input item is a recommended value. *9 the v 5 voltage adjusting circuit is adjusted within the voltage follower operating voltage range. *10 this is the internal voltage reference supply for the v 5 voltage regulator circuit. the thermal slope v reg of the S1D15710 series is about 0.05%/ c. *11 and *12 indicate the current dissipated by a single ic at built-in oscillator circuit used, 1/9 bias, and display on. does not include the current due to the lcd panel capacity and wireing capacity. applicable only when there is no access from the mpu. *12 when the v 5 voltage adjusting built-in resistor is used relationships between the oscillating frequency f osc , display clock frequency f cl , and liquid crystal frame frequency f fr 10. dc characteristics
50 epson S1D15710 series (rev. 1.1c) timing characteristics system bus read/write characteristics 1 (80 series mpu) a0 cs1 (cs2="1") wr, rd d0 to d7 (write) d0 to d7 (read) t acc8 t oh8 t ds8 t cyc8 t ah8 t aw8 t cclr , t cclw t cchr , t cchw t dh8 cs1 (cs2="1") wr, rd *1 *2 figure 28 table 26 [v dd =4.5v to 5.5v, ta= C 40 to +85 c] specification value item signal symbol condition min. max. unit address hold time a0 t ah8 0 ns address setup time t aw8 0 system cycle time a0 t cyc8 333 control low pulse width (write) wr t cclw 30 control low pulse width (read) rd t cclr 70 control high pulse width (write) wr t cchw 30 control high pulse width (read) rd t cchr 30 data setup time d0 to d7 t ds8 30 data hold time t dh8 10 rd access time t acc8 c l =100pf 70 output disable time t oh8 550 *1 is set when cs is low and access is made with wr and rd. *2 is used when wr and rd are low and accessed with cs. 10. dc characteristics
S1D15710 series (rev. 1.1c) epson 51 table 28 [v dd =1.8v to 2.7v, ta= C 40 to +85 c] specification value item signal symbol condition min. max. unit address hold time a0 t ah8 0 ns address setup time t aw8 0 system cycle time a0 t cyc8 1000 control low pulse width (write) wr t cclw 120 control low pulse width (read) rd t cclr 240 control high pulse width (write) wr t cchw 120 control high pulse width (read) rd t cchr 120 data setup time d0 to d7 t ds8 80 data hold time t dh8 30 rd access time t acc8 c l =100pf 280 output disable time t oh8 10 200 *1. this is the case of accessing by wr and rd when cs1 = low. *2. this is the case of accessing by cs1 when wr and rd = low. *3 the rise and fall times ( t r and t f ) of the input signal are specified for less than 15 ns. when using the system cycle time at high speed, they are specified for ( t r + t f ) ( t cyc8 t cclw t cchw ) or ( t r + t f ) ( t cyc8 t cclr t cchr ). *4 all timings are specified based on the 20 and 80% of v dd . *5 t cclw and t cclr are specified for the overlap period when cs1 is at low (cs2= high) level and wr, rd are at the low level. table 27 [v dd =2.7v to 4.5v, ta= C 40 to +85 c] specification value item signal symbol condition min. max. unit address hold time a0 t ah8 0 ns address setup time t aw8 0 system cycle time a0 t cyc8 500 control low pulse width (write) wr t cclw 60 control low pulse width (read) rd t cclr 120 control high pulse width (write) wr t cchw 60 control high pulse width (read) rd t cchr 60 data setup time d0 to d7 t ds8 40 data hold time t dh8 15 rd access time t acc8 c l =100pf 140 output disable time t oh8 10 100 10. dc characteristics
52 epson S1D15710 series (rev. 1.1c) system bus read/write characteristics 2 (68 series mpu) a0 r/w cs1 (cs2="1") e d0 to d7 (write) d0 to d7 (read) t acc6 t oh6 t ds6 t cyc6 t ah6 t aw6 t ewhr , t ewhw t ewlr , t ewlw t dh6 cs1 (cs2="1") e *1 *2 figure 29 table 29 [v dd =4.5v to 5.5v, ta= C 40 to +85 c] specification value item signal symbol condition min. max. unit address hold time a0 t ah6 0 ns address setup time t aw6 0 system cycle time t cyc6 333 data setup time d0 to d7 t ds6 30 data hold time t dh6 10 access time t acc6 c l =100pf 70 output disable time t oh6 10 50 enable high pulse read e t ewhr 70 width write t ewhw 30 enable low pulse read e t ewlr 30 width write t ewlw 30 *1 is set when cs is low and access is made with e. *2 is used when e is high and access is made with cs. 10. dc characteristics
S1D15710 series (rev. 1.1c) epson 53 table 30 [v dd =2.7v to 4.5v, ta= C 40 to +85 c] specification value item signal symbol condition min. max. unit address hold time a0 t ah6 0 ns address setup time t aw6 0 system cycle time t cyc6 500 data setup time d0 to d7 t ds6 40 data hold time t dh6 15 access time t acc6 c l =100pf 140 output disable time t oh6 10 100 enable high pulse read e t ewhr 120 width write t ewhw 60 enable low pulse read e t ewlr 60 width write t ewlw 60 table 31 [v dd =1.8v to 2.7v, ta= C 40 to +85 c] specification value item signal symbol condition min. max. unit address hold time a0 t ah6 0 ns address setup time t aw6 0 system cycle time t cyc6 1000 data setup time d0 to d7 t ds6 80 data hold time t dh6 30 access time t acc6 c l =100pf 280 output disable time t oh6 10 200 enable high pulse read e t ewhr 240 width write t ewhw 120 enable low pulse read e t ewlr 120 width write t ewlw 120 *1 this is the case of accessing by e when cs1 = low. *2 this is the case of accessing by cs1 when e = high. *3 the rise and fall times ( t r and t f ) of the input signal are specified for less than 15 ns. when using the system cycle time at high speed, they are specified for ( t r + t f ) ( t cyc6 t ewlw t ewhw ) or (t r +t f ) ( t cyc6 t ewlr t ewhr ). *4 all timings are specified based on the 20 and 80% of v dd . *5 t ewlw and t ewlr are specified for the overlap period when cs1 is at low (cs2 = high) level and e is at the high level. 10. dc characteristics
54 epson S1D15710 series (rev. 1.1c) serial interface t css t csh t sah t shw t sdh t sds t slw t f t r t scyc t sas cs1 (cs2="1") a0 scl si figure 30 table 32 [v dd =4.5v to 5.5v, ta= C 40 to +85 c] specification value item signal symbol condition min. max. unit serial clock cycle scl t scyc 200 ns scl high pulse width t shw 75 scl low pulse width t slw 75 address setup time a0 t sas 50 address hold time t sah 100 data setup time si t sds 50 data hold time t sdh 50 cs-scl time cs t css 100 t csh 100 table 33 [v dd =2.7v to 4.5v, ta= C 40 to +85 c] specification value item signal symbol condition min. max. unit serial clock cycle scl t scyc 250 ns scl high pulse width t shw 100 scl low pulse width t slw 100 address setup time a0 t sas 150 address hold time t sah 150 data setup time si t sds 100 data hold time t sdh 100 cs-scl time cs t css 150 t csh 150 10. dc characteristics
S1D15710 series (rev. 1.1c) epson 55 table 34 [v dd =1.8v to 2.7v, ta= C 40 to +85 c] specification value item signal symbol condition min. max. unit serial clock cycle scl t scyc 400 ns scl high pulse width t shw 150 scl low pulse width t slw 150 address setup time a0 t sas 250 address hold time t sah 250 data setup time si t sds 150 data hold time t sdh 150 cs-scl time cs t css 250 t csh 250 *1 the rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. *2 all timings are specified based on the 20 and 80% of v dd . display control output timing t dfr cl (out) fr t dsnc sync figure 31 table 35 [v dd =4.5v to 5.5v, ta= C 40 to +85 c] specification value item signal symbol condition min. typ. max. unit fr delay time fr t dfr c l =50pf 10 40 ns sync delay time sync t dsnc c l =50pf 10 40 ns table 36 [v dd =2.7v to 4.5v, ta= C 40 to +85 c] specification value item signal symbol condition min. typ. max. unit fr delay time fr t dfr c l =50pf 20 80 ns sync delay time sync t dsnc c l =50pf 20 80 ns table 37 [v dd =1.8v to 2.7v, ta= C 40 to +85 c] specification value item signal symbol condition min. typ. max. unit fr delay time fr t dfr c l =50pf 50 200 ns sync delay time sync t dsnc c l =50pf 50 200 ns *1 valid only when the master mode is selected. *2 all timings are specified based on the 20 and 80% of v dd . *3 pay attention not to cause delays of the timing signals cl, fr and sync to the salve side by wiring resistance, etc., while master/slave operations are in progress. if these delays occur, indication failures such as flickering may occur. 10. dc characteristics
56 epson S1D15710 series (rev. 1.1c) reset input timing t rw t r completion of reset resetting res internal state figure 32 table 38 [v dd =4.5v to 5.5v, ta= C 40 to +85 c] specification value item signal symbol condition min. typ. max. unit reset time t r 0.5 s reset low pulse width res t rw 0.5 table 39 [v dd =2.7v to 4.5v, ta= C 40 to +85 c] specification value item signal symbol condition min. typ. max. unit reset time t r 1 s reset low pulse width res t rw 1 table 40 [v dd =1.8v to 2.7v, ta= C 40 to +85 c] specification value item signal symbol condition min. typ. max. unit reset time t r 1.5 s reset low pulse width res t rw 1.5 *1 all timings are specified based on the 20 and 80% of v dd . 10. dc characteristics
S1D15710 series (rev. 1.1c) epson 57 11. microprocessor (mpu) interface: reference the S1D15710 series can directly be connected to the 80 system mpu and 68 series mup. it can also be operated with a fewer signal lines by using the serial interface. the S1D15710 series is used for the multiple chip configuration to expand the display area. in this case, it can select the ics that are accessed individually using the chip select signal. after the initialization using the res pin, the respective input pins of the S1D15710 series need to be controlled normally. 80 series mpu v dd v cc gnd decoder reset mpu a0 d0 to d7 rd wr res cs1 cs2 a0 d0 to d7 rd wr res a1 to a7 iorq v dd c86 p/s v ss v ss S1D15710 figure 33-1 68 series mpu v dd v cc gnd decoder reset mpu a0 d0 to d7 e r/w res cs1 cs2 a0 d0 to d7 e r/w res a1 to a15 vma v dd c86 p/s v ss v ss S1D15710 figure 33-2 serial interface v dd v cc gnd decoder reset mpu a0 si scl res cs1 cs2 a0 port 1 port 2 res a1 to a7 v dd or v ss c86 p/s v ss v ss S1D15710 figure 33-3 11. microprocessor (mpu) interface: reference
58 epson S1D15710 series (rev. 1.1c) 12. connection between lcd drivers: reference the S1D15710 series is used for the multiple chip configuration to easily expand the liquid crystal display area. use the same device (S1D15710 ***** /S1D15710 ***** ) for the master/slave. S1D15710 (master) ? S1D15710 (slave) v ss v dd m/s output input S1D15710 master m/s fr sync cl dof fr sync cl dof S1D15710 slave figure 34 12. connection between lcd drivers: reference
S1D15710 series (rev. 1.1c) epson 59 13. lcd panel wiring: reference the S1D15710 series is used for the multiple chip configuration to easily expand the liquid crystal display area. use the same device (S1D15710 ***** /S1D15710 ***** ) for the multiple chip configuration. 1-chip configuration 224 x 65 dots com seg com S1D15710 master figure 35-1 2-chip configuration 448 x 65 dots com com seg seg S1D15710 series master S1D15710 series slave figure 35-2 13. lcd panel wiring: reference
60 epson S1D15710 series (rev. 1.1c) 14. tcp pin layout sync frs fr cl dof cs1 cs2 res a0 wr,r/w rd, e d0 d1 d2 d3 d4 d5 d6, scl d7, si v dd v ss v ss2 v out cap3- cap1+ cap1- cap2- cap2+ v rs v dd v 1 v 2 v 3 v 4 v 5 v r m/s cls c86 p/s hpm irs frs sync com s com 63 com 33 com 32 seg 223 seg 222 seg 1 seg 0 com s com 0 com 30 com 31 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chip top view reference note) this tcp pin layout does not specify the tcp dimensions. 14. tcp pin layout
S1D15710 series (rev. 1.1c) epson 61 15. tcp dimensions sr=solder resist *dimension are defind after 25 c 60% 72h exposed. *failure devices are punch. ?at least die area is punch out completely. sl=slit 4 ic:sed157a-0b 3 2 2 (sl) (sl) (sl) (sl) 27.100 27.100 26.500 26.500 45 0.100 0.100 0.400 0.500 0.500 1.000 0.100 0.100 detail of b ( 20) detail of c ( 10) detail of a ( 20) 1.000 0.170 0.050 0.170 0.170 0.0575 0.170 min60 m 95 20 m (190 m) c b a max1.50 max1.50 max0.15 max0.80 max1.00 ... seg223 ... com32 ... com63 coms sync frs 28.5725 28.5725 28.3725 28.3725 0.07 56.050 nc x2 ... ... seg0 coms com0 ... com31 nc x2 nc irs hpm p/s c86 cls m/s vr v5 v4 v3 v2 v1 vdd vrs cap2+ cap2- cap1- cap1+ cap3- vout vss2 vss vdd d7(si) d6(scl) d5 d4 d3 d2 d1 d0 rd,e wr,r/w a0 res cs2 cs1 dof cl fr frs nc sync (mark) (sr) (sr) 8.560 13.190 12.800 11.000 5.260 8.800 1.700 0.05 1.500 (sl) (sl) (sr) (sr) (w:0.4,g:0.4) p0.8x(44-1)= (ic) (sl) (sl) (sl) (sl) 13.000 1.500 13.000 1.500 20.500 20.500 20.000 20.000 17.950 17.950 34.400 (encap. and mark area) 0.400 0.500 max19.650 16.650 13.000 1.500 13.000 0.05 1.500 (encap.and mark erea) (sl) (sl) (sl) (sl) (sl) (sl) (ic) 0.03 1.981 0.03 4.750 10.060 y (+) 9.060 7.560 5.560 4.800 4.800 max5.900 2.900 (mark) (mark) (sr) (sr) (w:0.095,g:0.095) p0.19x(296-1)= 0.2 69.950 x (+) -0.12 +0.08 63.949 max1.50 material ?base filem uplex-s 75 m ?copper foil 25 m ?plating sn ?no assigned position tolerance of solder resist 0.3 ?5 sproket holes (23.75mm) for 1 pattern max1.50 max0.15 max1.0 max0.8 cross sectional view of output outer lead 15. tcp dimensions
62 epson S1D15710 series (rev. 1.1c) 2. electrical characteristics specification value applicable item symbol condition min. typ. max. unit pin operating voltage svs (v dd standard) C 5.5 C 5.0 C 4.5 v svs1 (v dd standard) ta= C 40 c C 4.35 C 3.62 C 2.89 output voltage v sen (v dd standard) ta=25 c C 3.48 C 2.88 C 2.28 v v sen1 (v dd standard) ta=85 c C 2.92 C 2.20 C 1.47 output voltage v gra *1 9.4 11.4 13.4 mv/ c v sen1 temperature gradient output voltage ? vl *2 C 1.5 C 1.5 % v sen1 linearity output voltage t sen *3 100 CC ms v sen1 setup time operating current i sen ta=25 c C 40 150 a svs1 pin name i/o description number of pins svs1 power power terminal of the temperature sensor. apply compulsory 1 operation voltage to v dd . v sen1 o analog voltage output terminal of temperature sensor. monitor 1 the output voltage to v dd . 16. temperature sensor circuit both the S1D15710 * 10 ** and S1D15710 * 11 ** have built-in temperature sensor circuits with analog voltage output terminals having a temperature gradient of 11.4mv/ c (typ.). by controlling the liquid crystal drive voltage at v 5 by inputting an electric volume register value corresponding to the temperature sensor output value from the mpu enables liquid crystal to display appropriate light and shade over a wide range of temperatures. build a system to compensate for variations in the output voltage by feeding back the output voltage value sampled at a constant temperature to the mpu and store it as the standard voltage in order to achieve higher control of the liquid crystal drive voltage. 1. terminal description *terminals related to the temperature sensor circuit are allocated to test 1 and 2, and are named v sen1 for test1 and svs1 for test2. use the temperature sensor as indicated in the table below. when not in use, fix each terminal at high. 16. temperature sensor circuit
S1D15710 series (rev. 1.1c) epson 63 *notes: *1: slope of approximate line of typ. output voltage. *2: maximum deviation of output voltage curve and approximate line. when the output voltage difference between 40 c and 85 c is ? v sen , the difference between the approximate line and the output voltage value is ? diff and the maximum value is ? diff(max.), output voltage linearity ? v l will be expressed using the following formula: ? ? ? v diff max v l sen = ( ) . 100 output voltage v sen [v] (v dd =0[v] standard) ? v diff ? v diff (max.) ? v diff ? v diff ? v diff ? v sen =v sen (-40 c) C v sen (85 c) output voltage approximate line when becomes maximum at all temperatures it is defined as C 50 C 25 0 25 50 75 100 tem p erature ta [ c ] *3: waiting time until monitoring is enabled with stable output voltage after applying power voltage svs to terminal svs1. the output voltage needs to be sampled after a longer than standard waiting time. output voltage characteristics output voltage v sen [v] (v dd =0[v] standard) temperature ta[ c] C 50 C 5 C 4 C 3 C 2 C 1 0 C 25 0 25 50 75 100 max. typ. min. 16. temperature sensor circuit
64 epson S1D15710 series (rev. 1.1c) 3. output terminal load load capacity cl of v sen output terminal v sen1 should be under 100pf and load resistance rl higher than 1m ? . be careful not to build a current path between v ss in order to obtain an accurate output voltage value. v dd v dd v sen v sen S1D15710 series cl rl 16. temperature sensor circuit
S1D15710 series (rev. 1.1c) epson 65 17. notes the following points should be noted when this development specification is used: please be advised on the following points in use of this development specification. 1. this development specification is subject to change without previous notice. 2. this development specification does not guarantee or furnish the industrial property right not its execution. application examples in this development specification are intended to ensure your better understanding of the product. thus the manufacturer shall not be liable for any trouble arising in your circuits from using such application example. numerical values provided in the property table of this manual are represented with their magnitude on the numerical line. 3. no part of this development specification may not be reproduced, copied or used for commercial purpose without a written permission from the manufacturer. in handling of semiconductor devices, your attention is required to following points. [precaution on light] property of semiconductor devices may be affected when they are exposed to light, possibly resulting in malfunctioning of the ics. to prevent such malfunctioning of the ics mounted on the boards or products, make sure that: (1) your design and mounting layout done are so that the ic is not exposed to light in actual use. (2) the ic is protected from light in the inspection process. (3) the ic is protected from light in its front, rear and side faces. attention to cog module when this ic is used as chip on glass (cog) module, it needs the greatest care as follows, because the resistance of ito wire inserted between ic and external input / output pins may influence the display quality. (1) the resistance of ito wire connected to external capacitor must be as low as possible. (2) the resistance of ito wire connected to power source must be as low as possible. 17. notes
international sales operations america epson electronics america, inc. headquarters 150 river oaks parkway san jose, ca 95134, u.s.a. phone: +1-800-228-3964 fax: +1-408-922-0238 sales offices west 1960 e.grand avenue flr 2 el segundo, ca 90245, u.s.a. phone: +1-800-249-7730 fax: +1-310-955-5400 central 101 virginia street, suite 290 crystal lake, il 60014, u.s.a. phone: +1-800-853-3588 fax: +1-815-455-7633 northeast 301 edgewater place, suite 210 wakefield, ma 01880, u.s.a. phone: +1-800-922-7667 fax: +1-781-246-5443 southeast 3010 royal blvd. south, suite 170 alpharetta, ga 30005, u.s.a. phone: +1-877-332-0020 fax: +1-770-777-2637 europe epson europe electronics gmbh headquarters riesstrasse 15 80992 munich, germany phone: +49-89-14005-0 fax: +49-89-14005-110 dsseldorf branch office altstadtstrasse 176 51379 leverkusen, germany phone: +49-2171-5045-0 fax: +49-2171-5045-10 french branch office 1 avenue de l ? atlantique, lp 915 les conquerants z.a. de courtaboeuf 2, f-91976 les ulis cedex, france phone: +33-1-64862350 fax: +33-1-64862355 barcelona branch office barcelona design center edificio testa, c/alcalde ba rnils 64-68, modulo c 2a planta e-08190 sant cugat del vall s, spain phone: +34-93-544-2490 fax: +34-93-544-2491 uk & ireland branch office 8 the square, stockley park, uxbridge middx ub11 1fw, united kingdom phone: +44-1295-750-216/+44-1342-824451 fax: +44-89-14005 446/447 scotland design center integration house, the alba campus livingston west lothian, eh54 7eg, scotland phone: +44-1506-605040 fax: +44-1506-605041 asia epson (china) co., ltd. 23f, beijing silver tower 2# north rd dongsanhuan chaoyang district, beijing, china phone: +86-10-6410-6655 fax: +86-10-6410-7320 shanghai branch 7f, high-tech bldg., 900, yishan road, shanghai 200233, china phone: +86-21-5423-5522 fax: +86-21-5423-5512 epson electronic technology development (shenzhen) co., ltd 12/f, dawning mansion, keji 12 road south, hi-tech park, shenzhen, china phone: +86-755-2699-3828 fax: +86-755-2699-3838 epson hong kong ltd. 20/f., harbour centre, 25 harbour road wanchai, hong kong phone: +852-2585-4600 fax: +852-2827-4346 telex: 65542 epsco hx epson taiwan technology & trading ltd. 14f, no. 7, song ren road, taipei 110 phone: +886-2-8786-6688 fax: +886-2-8786-6677 hsinchu office no. 99, jiangong road, hsinchu city 300 phone: +886-3-573-9900 fax: +886-3-573-9169 epson singapore pte., ltd. 401 commonwealth drive, #07-01 haw par technocentre, singapore 149598 phone: +65-6586-3100 fax: +65-6472-4291 epson trading (malaysia) sdn. bhd. ed penang office 8-1-04, sunny point complex, jalan batu uban 11700 pulau penang, malaysia phone: +60-4-6589243 fax: +60-4-6589249 seiko epson corporation korea office 50f, kli 63 bldg., 60 yoido-dong youngdeungpo-ku, seoul, 150-763, korea phone: +82-2-784-6027 fax: +82-2-767-3677 gumi office 6f, good morning securities bldg., 56 songjeong-dong, gumi-city, seoul, 730-090, korea phone: +82-54-454-6027 fax: +82-54-454-6093 - japan - seiko epson corporation electronic devices marketing & sales div. ed international sales dept. 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117
in pursuit of ?aving?technology , epson electronic devices. our lineup of semiconductors, displays and quartz devices assists in creating the products of our customers?dreams. epson is energy savings.
document code : 404948201 first issue december, 1992 u printed december, 2004 in japan h a epson electronic devices website electronic devices marketing division seiko epson corporation http://www.epsondevice.com/ S1D15710 series technical manual
international sales operations america epson electronics america, inc. headquarters 150 river oaks parkway san jose, ca 95134, u.s.a. phone: +1-800-228-3964 fax: +1-408-922-0238 sales offices west 1960 e.grand avenue flr 2 el segundo, ca 90245, u.s.a. phone: +1-800-249-7730 fax: +1-310-955-5400 central 101 virginia street, suite 290 crystal lake, il 60014, u.s.a. phone: +1-800-853-3588 fax: +1-815-455-7633 northeast 301 edgewater place, suite 210 wakefield, ma 01880, u.s.a. phone: +1-800-922-7667 fax: +1-781-246-5443 southeast 3010 royal blvd. south, suite 170 alpharetta, ga 30005, u.s.a. phone: +1-877-332-0020 fax: +1-770-777-2637 europe epson europe electronics gmbh headquarters riesstrasse 15 80992 munich, germany phone: +49-89-14005-0 fax: +49-89-14005-110 dsseldorf branch office altstadtstrasse 176 51379 leverkusen, germany phone: +49-2171-5045-0 fax: +49-2171-5045-10 french branch office 1 avenue de l ? atlantique, lp 915 les conquerants z.a. de courtaboeuf 2, f-91976 les ulis cedex, france phone: +33-1-64862350 fax: +33-1-64862355 barcelona branch office barcelona design center edificio testa, c/alcalde barnils 64-68, modulo c 2a planta e-08190 sant cugat del vall s, spain phone: +34-93-544-2490 fax: +34-93-544-2491 uk & ireland branch office 8 the square, stockley park, uxbridge middx ub11 1fw, united kingdom phone: +44-1295-750-216/+44-1342-824451 fax: +44-89-14005 446/447 scotland design center integration house, the alba campus livingston west lothian, eh54 7eg, scotland phone: +44-1506-605040 fax: +44-1506-605041 asia epson (china) co., ltd. 23f, beijing silver tower 2# north rd dongsanhuan chaoyang district, beijing, china phone: +86-10-6410-6655 fax: +86-10-6410-7320 shanghai branch 7f, high-tech bldg., 900, yishan road, shanghai 200233, china phone: +86-21-5423-5522 fax: +86-21-5423-5512 epson hong kong ltd. 20/f., harbour centre, 25 harbour road wanchai, hong kong phone: +852-2585-4600 fax: +852-2827-4346 telex: 65542 epsco hx epson electronic technology development (shenzhen) ltd. 12/f, dawning mansion, keji south 12th road, hi- tech park, shenzhen phone: +86-755-2699-3828 fax: +86-755-2699-3838 epson taiwan technology & trading ltd. 14f, no. 7, song ren road, taipei 110 phone: +886-2-8786-6688 fax: +886-2-8786-6677 hsinchu office no. 99, jiangong road, hsinchu city 300 phone: +886-3-573-9900 fax: +886-3-573-9169 epson singapore pte., ltd. 1 harbourfront place, #03-02 harbourfront tower one, singapore 098633 phone: +65-6586-5500 fax: +65-6271-3182 seiko epson corporation korea office 50f, kli 63 bldg., 60 yoido-dong youngdeungpo-ku, seoul, 150-763, korea phone: +82-2-784-6027 fax: +82-2-767-3677 gumi office 2f, grand b/d, 457-4 songjeong-dong, gumi-city, korea phone: +82-54-454-6027 fax: +82-54-454-6093 seiko epson corporation semiconductor operations division ic sales dept. ic marketing group 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 document code: 404948302 first issue february 2004 h printed october 2005 in japan

▲Up To Search▲

Price & Availability of S1D15710

	To Download S1D15710 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .